SLVSGN5A
October 2022 – November 2025
LM51231-Q1
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Typical Characteristics
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagram
6.3
Feature Description
6.3.1
Device Enable/Disable (EN, VH Pin)
6.3.2
High Voltage VCC Regulator (BIAS, VCC Pin)
6.3.3
Light Load Switching Mode Selection (MODE Pin)
6.3.4
VOUT Range Selection (RANGE Pin)
6.3.5
Line Undervoltage Lockout (UVLO Pin)
6.3.6
Fast Restart using VCC HOLD (VH Pin)
6.3.7
Adjustable Output Regulation Target (VOUT, TRK, VREF Pin)
6.3.8
Overvoltage Protection (VOUT Pin)
6.3.9
Power Good Indicator (PGOOD Pin)
6.3.10
Dynamically Programmable Switching Frequency (RT)
6.3.11
External Clock Synchronization (SYNC Pin)
6.3.12
Programmable Spread Spectrum (DITHER Pin)
6.3.13
Programmable Soft-start (SS Pin)
6.3.14
Wide Bandwidth Transconductance Error Amplifier and PWM (TRK, COMP Pin)
6.3.15
Current Sensing and Slope Compensation (CSP, CSN Pin)
6.3.16
Constant Peak Current Limit (CSP, CSN Pin)
6.3.17
Maximum Duty Cycle and Minimum Controllable On-time Limits
6.3.18
MOSFET Drivers, Integrated Boot Diode, and Hiccup Mode Fault Protection (LO, HO, HB Pin)
6.3.19
Thermal Shutdown Protection
6.4
Device Functional Modes
6.4.1
Device Status
6.4.1.1
Shutdown Mode
6.4.1.2
Configuration Mode
6.4.1.3
Active Mode
6.4.1.4
Bypass Mode
6.4.1.4.1
Bypass DE mode
6.4.1.4.2
Bypass FPWM
6.4.2
Light Load Switching Mode
6.4.2.1
Forced PWM (FPWM) Mode
6.4.2.2
Diode Emulation (DE) Mode
6.4.2.3
Forced Diode Emulation Operation in FPWM Mode
7
Application and Implementation
7.1
Application Information
7.2
Typical Application
7.2.1
Design Requirements
7.2.2
Detailed Design Procedure
7.2.3
Application Ideas
7.2.4
Application Curves
7.3
System Example
7.4
Power Supply Recommendations
7.5
Layout
7.5.1
Layout Guidelines
7.5.2
Layout Example
8
Device and Documentation Support
8.1
Receiving Notification of Documentation Updates
8.2
Support Resources
8.3
Trademarks
8.4
Electrostatic Discharge Caution
8.5
Glossary
9
Revision History
10
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RGR|20
MPQF239A
Thermal pad, mechanical data (Package|Pins)
RGR|20
QFND664
Orderable Information
slvsgn5a_oa
slvsgn5a_pm
5.6
Typical Characteristics
Figure 5-1
Frequency vs RT Resistance
Figure 5-3
RT Frequency vs Temperature
(RT = 220kΩ, f
SW
= 100kHz)
Figure 5-5
V
BIAS
vs I
BIAS
(active mode)
Figure 5-7
V
VOUT
vs I
VOUT
(bypass mode)
Figure 5-9
V
VCC
vs I
VCC
Figure 5-11
Peak current limit threshold V
CLTH
vs Temperature, V
CSP
= 3V
Figure 5-13
I
CSP
vs V
CSP
(active mode)
Figure 5-15
V
REF
vs Temperature
Figure 5-17
DMAX vs Switching Frequency
Figure 5-2
RT Frequency vs Temperature
(RT = 9.09kΩ, f
SW
= 2.2MHz)
Figure 5-4
V
BIAS
vs I
BIAS
(shutdown mode)
Figure 5-6
Bypass DEM
Figure 5-8
V
BIAS
vs V
VCC
Figure 5-10
Peak current limit threshold V
CLTH
vs V
CSP
Figure 5-12
Bypass forward current threshold, V
CS-FWD
vs Temperature , V
CSP
= 3V
Figure 5-14
I
CSP
vs temperature (active mode)
V
CSP
= 3V
Figure 5-16
V
VCC
vs Peak Driver Current