SNVSB75D December   2018  – January 2021 LM5155 , LM51551

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Line Undervoltage Lockout (UVLO/SYNC Pin)
      2. 9.3.2  High Voltage VCC Regulator (BIAS, VCC Pin)
      3. 9.3.3  Soft Start (SS Pin)
      4. 9.3.4  Switching Frequency (RT Pin)
      5. 9.3.5  Clock Synchronization (UVLO/SYNC Pin)
      6. 9.3.6  Current Sense and Slope Compensation (CS Pin)
      7. 9.3.7  Current Limit and Minimum On-time (CS Pin)
      8. 9.3.8  Feedback and Error Amplifier (FB, COMP Pin)
      9. 9.3.9  Power-Good Indicator (PGOOD Pin)
      10. 9.3.10 Hiccup Mode Overload Protection (LM51551 Only)
      11. 9.3.11 Maximum Duty Cycle Limit and Minimum Input Supply Voltage
      12. 9.3.12 MOSFET Driver (GATE Pin)
      13. 9.3.13 Overvoltage Protection (OVP)
      14. 9.3.14 Thermal Shutdown (TSD)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Shutdown Mode
      2. 9.4.2 Standby Mode
      3. 9.4.3 Run Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Custom Design With WEBENCH® Tools
        2. 10.2.2.2 Recommended Components
        3. 10.2.2.3 Inductor Selection (LM)
        4. 10.2.2.4 Output Capacitor (COUT)
        5. 10.2.2.5 Input Capacitor
        6. 10.2.2.6 MOSFET Selection
        7. 10.2.2.7 Diode Selection
        8. 10.2.2.8 Efficiency Estimation
      3. 10.2.3 Application Curve
    3. 10.3 System Examples
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
      2. 13.1.2 Development Support
        1. 13.1.2.1 Custom Design With WEBENCH® Tools
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Efficiency Estimation

The total loss of the boost converter (PTOTAL) can be expressed as the sum of the losses in the device (PIC), MOSFET power losses (PQ), diode power losses (PD), inductor power losses (PL), and the loss in the sense resistor (PRS).

Equation 19. GUID-CABF347A-F245-4749-81E9-ACDB480530F6-low.gif

PIC can be separated into gate driving loss (PG) and the losses caused by quiescent current (PIQ).

Equation 20. GUID-062DDBC3-33FD-4E15-ADBB-14A4E59E436F-low.gif

Each power loss is approximately calculated as follows:

Equation 21. GUID-5BF790DA-4652-4E41-BFD9-0FFFA34FA949-low.gif
Equation 22. GUID-83B4F02A-F210-4EAB-87D0-28FE8C32819A-low.gif

IVIN and IVOUT values in each mode can be found in the supply current section of Section 8.5.

PQ can be separated into switching loss (PQ(SW)) and conduction loss (PQ(COND)).

Equation 23. GUID-9FF1B632-8649-417F-9F94-3A1B97BED250-low.gif

Each power loss is approximately calculated as follows:

Equation 24. GUID-CAFD2B69-7E00-4DEA-97F3-0F5490D98B5B-low.gif

tR and tF are the rise and fall times of the low-side N-channel MOSFET device. ISUPPLY is the input supply current of the boost converter.

Equation 25. GUID-F4FCD3E7-0FDC-4146-AFAB-845A269D1866-low.gif

RDS(ON) is the on-resistance of the MOSFET and is specified in the MOSFET data sheet. Consider the RDS(ON) increase due to self-heating.

PD can be separated into diode conduction loss (PVF) and reverse recovery loss (PRR).

Equation 26. GUID-413F1B60-4C29-4F87-A074-9E16AEE830C1-low.gif

Each power loss is approximately calculated as follows:

Equation 27. GUID-A066B523-7707-4985-BFA7-6D82724D2AAE-low.gif
Equation 28. GUID-668FFECD-D54F-4EF7-A8A7-7B76CD19B426-low.gif

QRR is the reverse recovery charge of the diode and is specified in the diode data sheet. Reverse recovery characteristics of the diode strongly affect efficiency, especially when the output voltage is high.

PL is the sum of DCR loss (PDCR) and AC core loss (PAC). DCR is the DC resistance of inductor which is mentioned in the inductor data sheet.

Equation 29. GUID-C0D0176F-EC16-4BF3-8571-7BDD0C9F2AE9-low.gif

Each power loss is approximately calculated as follows:

Equation 30. GUID-C6FA6588-422D-42B1-B3A7-DB6DBCF0E774-low.gif
Equation 31. GUID-E11FC28D-6294-4117-9E83-3CE1DEC5FE88-low.gif
Equation 32. GUID-2A3FCA88-4131-4DC6-B84B-7750BE9D19CA-low.gif

∆I is the peak-to-peak inductor current ripple. K, α, and β are core dependent factors which can be provided by the inductor manufacturer.

PRS is calculated as follows:

Equation 33. GUID-6916A196-77A8-4001-89FC-3D3CE91EFD54-low.gif

Efficiency of the power converter can be estimated as follows:

Equation 34. GUID-37E7BCAB-EF40-441D-970A-F1C753F2D7B6-low.gif