SNVSB75D December   2018  – January 2021 LM5155 , LM51551

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Line Undervoltage Lockout (UVLO/SYNC Pin)
      2. 9.3.2  High Voltage VCC Regulator (BIAS, VCC Pin)
      3. 9.3.3  Soft Start (SS Pin)
      4. 9.3.4  Switching Frequency (RT Pin)
      5. 9.3.5  Clock Synchronization (UVLO/SYNC Pin)
      6. 9.3.6  Current Sense and Slope Compensation (CS Pin)
      7. 9.3.7  Current Limit and Minimum On-time (CS Pin)
      8. 9.3.8  Feedback and Error Amplifier (FB, COMP Pin)
      9. 9.3.9  Power-Good Indicator (PGOOD Pin)
      10. 9.3.10 Hiccup Mode Overload Protection (LM51551 Only)
      11. 9.3.11 Maximum Duty Cycle Limit and Minimum Input Supply Voltage
      12. 9.3.12 MOSFET Driver (GATE Pin)
      13. 9.3.13 Overvoltage Protection (OVP)
      14. 9.3.14 Thermal Shutdown (TSD)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Shutdown Mode
      2. 9.4.2 Standby Mode
      3. 9.4.3 Run Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Custom Design With WEBENCH® Tools
        2. 10.2.2.2 Recommended Components
        3. 10.2.2.3 Inductor Selection (LM)
        4. 10.2.2.4 Output Capacitor (COUT)
        5. 10.2.2.5 Input Capacitor
        6. 10.2.2.6 MOSFET Selection
        7. 10.2.2.7 Diode Selection
        8. 10.2.2.8 Efficiency Estimation
      3. 10.2.3 Application Curve
    3. 10.3 System Examples
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
      2. 13.1.2 Development Support
        1. 13.1.2.1 Custom Design With WEBENCH® Tools
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout Guidelines

The performance of switching converters heavily depends on the quality of the PCB layout. The following guidelines will help users design a PCB with the best power conversion performance, thermal performance, and minimize generation of unwanted EMI.

  • Put the Q1, D1, and RS components on the board first.
  • Use a small size ceramic capacitor for COUT.
  • Make the switching loop (COUT to D1 to Q1 to RS to COUT) as small as possible.
  • Leave a copper area near the D1 diode for thermal dissipation.
  • Put the device near the RS resistor.
  • Put the CVCC capacitor as near the device as possible between the VCC and PGND pins.
  • Use a wide and short trace to connect the PGND pin directly to the center of the sense resistor.
  • Connect the CS pin to the center of the sense resistor. If necessary, use vias.
  • Connect a filter capacitor between CS pin and power ground trace.
  • Connect the COMP pin to the compensation components (RCOMP and CCOMP).
  • Connect the CCOMP capacitor to the power ground trace.
  • Connect the AGND pin directly to the analog ground plane. Connect the AGND pin to the RUVLOB, RT, CSS, and RFBB components.
  • Connect the exposed pad to the AGND and PGND pins under the device.
  • Connect the GATE pin to the gate of the Q1 FET. If necessary, use vias.
  • Make the switching signal loop (GATE to Q1 to RS to PGND to GATE) as small as possible.
  • Add several vias under the exposed pad to help conduct heat away from the device. Connect the vias to a large ground plane on the bottom layer.