10.1 Layout Guidelines
A proper layout is essential for optimum performance of the circuit. In particular, observe the following guidelines:
- CIN: The loop consisting of input capacitor (CIN), VIN pin and PGND pin carries the switching current. The input capacitor must be placed close to the IC, directly across VIN and PGND pins, and the connections to these two pins must be direct to minimize the switching power loop area. In general, it is not possible to place all of input capacitances near the IC. A good layout practice includes placing the bulk capacitor(s) as close as possible to the VIN pin (see Figure 35). A bypass capacitor measuring 0.1 µF must be placed directly across VIN and PGND (pin 3 and 2, respectively), as close as possible to the IC while complying with all layout design rules.
- CVCC and CBST: The VCC and bootstrap (BST) bypass capacitors supply switching currents to the high-side and low-side gate drivers. These two capacitors must also be placed as close to the IC as possible, and the connecting trace length and loop area must be minimized (see Figure 35).
- The feedback trace carries the output voltage information and a small ripple component that is necessary for proper operation of the LM5160-Q1. Therefore, take care while routing the feedback trace to avoid coupling any noise into this pin. In particular, the feedback trace must be short and not run close to magnetic components, or parallel to any other switching trace.
- SW trace: The SW node switches rapidly between VIN and GND every cycle and is therefore a source of noise. The SW node copper area must be minimized. In particular, the SW node must not be inadvertently connected to a copper plane or pour.