SNVSC55 September   2025 LM51770-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Gate Driver Rise Time and Fall Time
    2. 7.2 Gate Driver Dead (Transition) Time
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Power-On Reset (POR System)
      2. 8.3.2  Buck-Boost Control Scheme
        1. 8.3.2.1 Boost Mode
        2. 8.3.2.2 Buck Mode
        3. 8.3.2.3 Buck-Boost Mode
      3. 8.3.3  Power Save Mode
      4. 8.3.4  Supply Voltage Selection – VMAX Switch
      5. 8.3.5  Enable and Undervoltage Lockout
      6. 8.3.6  Oscillator Frequency Selection
      7. 8.3.7  Frequency Synchronization
      8. 8.3.8  Voltage Regulation Loop
      9. 8.3.9  Output Voltage Tracking
      10. 8.3.10 Slope Compensation
      11. 8.3.11 Configurable Soft Start
      12. 8.3.12 Peak Current Sensor
      13. 8.3.13 Current Monitoring and Current Limit Control Loop
      14. 8.3.14 Short Circuit - Hiccup Protection
      15. 8.3.15 nFLT Pin and Protections
      16. 8.3.16 Device Configuration Pin
      17. 8.3.17 Dual Random Spread Spectrum – DRSS
      18. 8.3.18 Gate Driver
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Custom Design with WEBENCH Tools
        2. 9.2.2.2  Frequency
        3. 9.2.2.3  Feedback Divider
        4. 9.2.2.4  Inductor and Current Sense Resistor Selection
        5. 9.2.2.5  Slope Compensation
        6. 9.2.2.6  Output Capacitor
        7. 9.2.2.7  Input Capacitor
        8. 9.2.2.8  UVLO Divider
        9. 9.2.2.9  Soft-Start Capacitor
        10. 9.2.2.10 MOSFETs QH1 and QL1
        11. 9.2.2.11 MOSFETs QH2 and QL2
        12. 9.2.2.12 Output Voltage Frequency Compensation
        13. 9.2.2.13 External Component Selection
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Bi-Directional Power Backup
      2. 9.3.2 Parallel (Multiphase) Operation
      3. 9.3.3 External Gate Driver with Logic Level High Side Gate Signals
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
        1. 9.5.1.1 Power Stage Layout
        2. 9.5.1.2 Gate Driver Layout
        3. 9.5.1.3 Controller Layout
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
        1. 10.1.2.1 Custom Design with WEBENCH Tools
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1.     86

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DCP|38
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2.4 Inductor and Current Sense Resistor Selection

For boost mode, the inductor selection is based on limiting the peak-to-peak current ripple, ΔIL, to approximately 20% of the maximum inductor current at the minimum input voltage. The target inductance for boost mode is:

Equation 20. L BOOST =   V IN ( MIN ) 2 × V OUT - V IN ( MIN ) 0 .2 ×   I OUT MAX ×   f SW ×   V OUT 2 =   2 .21 μH

For this application, an inductor with 1.8μH was selected.

Select the current sense resistor for the peak inductor current to not hit the over current limit at maximum output current. For that the peak inductor current needs to be calculated with the sum of the average and ripple current through the inductor.

The maximum peak to peak inductor current occurs at minimum input voltage and is given by:

Equation 21. I L ( P E A K , P E A K ) = 1 - V I N M I N V O U T × V I N ( M I N ) L × f S W = 5.23   A
The average input current at the maximum output current with an estimated efficiency of 95% is calculated by:
Equation 22. I I N , A V G ( M A X ) = V O U T × I O U T M A X 95 % × V I N M I N = 22.5   A
For the current sense Resistor a margin of 20% is considered to have enough headroom for the dynamic responses, for example, load step regulation. To enable the maximum output current to be delivered, the minimum level of the peak current limit threshold is used.
Equation 23. R C S = V th+(CSB-CSA),min I I N , A V G M A X + 1 2 I L ( P E A K , P E A K ) × 1.2 = 1.41   m Ω

The standard value of RCS = 1mΩ with 3 times 3mΩ is selected. With the 3 resistors in parallel it also reduces the parasitic inductance.

The maximum power dissipation in RCS happens at VIN(MAX):

Equation 24. P R CS ( MAX ) =   V th+(CSB-CSA),max R CS 2 ×   R CS ×   1 - V OUT V IN MAX =   1 .84 W
Therefore, for the 3 resistors in parallel a sense resistor with 1W power rating is sufficient for this application.

Add a filter network to attenuate noise in the CSA and CSB sense lines. For most applications it is recommended to use a filter resistance RDIFF1 and RDIFF2 of 10Ω. Calculate the capacitance CDIFF for the filter with Equation 16. In this configuration 180pF is used.