SNVSC55 September   2025 LM51770-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Gate Driver Rise Time and Fall Time
    2. 7.2 Gate Driver Dead (Transition) Time
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Power-On Reset (POR System)
      2. 8.3.2  Buck-Boost Control Scheme
        1. 8.3.2.1 Boost Mode
        2. 8.3.2.2 Buck Mode
        3. 8.3.2.3 Buck-Boost Mode
      3. 8.3.3  Power Save Mode
      4. 8.3.4  Supply Voltage Selection – VMAX Switch
      5. 8.3.5  Enable and Undervoltage Lockout
      6. 8.3.6  Oscillator Frequency Selection
      7. 8.3.7  Frequency Synchronization
      8. 8.3.8  Voltage Regulation Loop
      9. 8.3.9  Output Voltage Tracking
      10. 8.3.10 Slope Compensation
      11. 8.3.11 Configurable Soft Start
      12. 8.3.12 Peak Current Sensor
      13. 8.3.13 Current Monitoring and Current Limit Control Loop
      14. 8.3.14 Short Circuit - Hiccup Protection
      15. 8.3.15 nFLT Pin and Protections
      16. 8.3.16 Device Configuration Pin
      17. 8.3.17 Dual Random Spread Spectrum – DRSS
      18. 8.3.18 Gate Driver
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Custom Design with WEBENCH Tools
        2. 9.2.2.2  Frequency
        3. 9.2.2.3  Feedback Divider
        4. 9.2.2.4  Inductor and Current Sense Resistor Selection
        5. 9.2.2.5  Slope Compensation
        6. 9.2.2.6  Output Capacitor
        7. 9.2.2.7  Input Capacitor
        8. 9.2.2.8  UVLO Divider
        9. 9.2.2.9  Soft-Start Capacitor
        10. 9.2.2.10 MOSFETs QH1 and QL1
        11. 9.2.2.11 MOSFETs QH2 and QL2
        12. 9.2.2.12 Output Voltage Frequency Compensation
        13. 9.2.2.13 External Component Selection
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Bi-Directional Power Backup
      2. 9.3.2 Parallel (Multiphase) Operation
      3. 9.3.3 External Gate Driver with Logic Level High Side Gate Signals
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
        1. 9.5.1.1 Power Stage Layout
        2. 9.5.1.2 Gate Driver Layout
        3. 9.5.1.3 Controller Layout
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
        1. 10.1.2.1 Custom Design with WEBENCH Tools
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1.     86

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DCP|38
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.18 Gate Driver

The LM51770-Q1 features four internal logic-level nMOS gate drivers. The drivers maintain the high frequency switching of both half bridges needed for a buck-boost operation. If the device is in boost or buck mode, the other half bridge high-side switch needs to be permanent on. The internal gate drivers support this by sharing the current from the other half bridge, which is switching. Therefore, no additional internal charge pump is needed and the device has a low quiescent current rating. Due to the high drive current, it supports a wide range of external power FETs as well as a parallel operation of them.

The LO and HO outputs are protected with a shoot-through protection, which allows for both outputs to not be turned on at the same time. If the PWM modulation logic of the buck-boost turns the LOx pin off, the HOx pin is not turned on until the following are all true (AND not OR) true:

  1. A minimum internal transition time (tt(dead)) is reached.
  2. The voltage on the LOx pin drops below the detection threshold VTH(GATEOUT).
This behavior is maintained and vice versa if the HOx pin turns off first.

The high-side supply voltage for the gate driver are monitored by an additional bootstrap UVLO comparator. This comparator monitors the differential voltage between SWx and HBx. If the voltage drops below the threshold the buck-boost converter operation turns off. The device restarts automatically once the positive going threshold is reached with the soft-start scheme.

Additionally, the LM51770-Q1 monitors the upper voltage between SWx and HBx. If this voltage exceeds the threshold voltage of the clamping circuit, it activates a internal current source to pull the voltage down.


LM51770-Q1 Functional Block Diagram Gate Driver
Figure 8-21 Functional Block Diagram Gate Driver

External Gate Driver Support

The LM51770-Q1 supports operation with an external gate driver using the HOx_LL pins. These pins provide the two high-side gate drive signals referenced to ground. By connecting the HOx_LL and LOx signals to an external gate driver, the external power FETs are controlled by the external gate driver. This feature is helpful if no logic level FET is available, and the application needs to drive gate voltages higher than the integrated gate drive provides.

Continue to place the external bootstrap capacitors on HBx because the internal current sense amplifier is supplied through these pins. Leave the HOx pin floating. Make sure the supply voltage V(extGD) for each external gate driver maintains the necessary requirements for a 4-switch Buck-Boost. An example of this is the 100% duty cycle, and the isolation between each side of the full-bridge. See the Simplified Schematic External Gate Driver support for a functional block diagram illustrating a possible connection for an example gate driver.

LM51770-Q1 Simplified Schematic External Gate Driver support Figure 8-22 Simplified Schematic External Gate Driver support