SNAS558M February   2000  – July 2016 LMC555

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Low-Power Dissipation
      2. 8.3.2 Various Packages and Compatibility
      3. 8.3.3 Operates in Both Astable and Monostable Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Monostable Operation
      2. 8.4.2 Astable Operation
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Frequency Divider
      1. 9.3.1 Design Requirements
      2. 9.3.2 Application Curve
    4. 9.4 Pulse Width Modulator
      1. 9.4.1 Design Requirements
      2. 9.4.2 Application Curve
    5. 9.5 Pulse Position Modulator
      1. 9.5.1 Design Requirements
      2. 9.5.2 Application Curve
    6. 9.6 50% Duty Cycle Oscillator
      1. 9.6.1 Design Requirements
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation SupportChanged layout of National Semiconductor Data Sheet to TI format
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Detailed Description

8.1 Overview

The LMC555 is a CMOS version of the industry standard 555 series general-purpose timers. In addition to the standard package (SOIC, VSSSOP, and PDIP) the LMC555 is also available in a chip-sized package (8-bump DSBGA) using TI’s DSBGA package technology. The LMC555 offers the same capability of generating accurate time delays and frequencies as the LM555 but with much lower power dissipation and supply current spikes. When operated as a one-shot, the time delay is precisely controlled by a single external resistor and capacitor. In the astable mode, the oscillation frequency and duty cycle are accurately set by two external resistors and one capacitor. The use of TI’s LMCMOS process extends both the frequency range and the low supply capability. The LMC555 is available in an 8-pin PDIP, SOIC, VSSOP, and 8-bump DSBGA package.

8.2 Functional Block Diagram

LMC555 LMC555.gif

8.3 Feature Description

8.3.1 Low-Power Dissipation

The LMC555 offers the same capability of generating accurate time delays and frequencies as the LM555 but with much lower power dissipation. A power dissipation of less than 0.2 mW can be achieved with a 1.5-V operating supply voltage and less than 1 mW with a 5-V operating supply voltage. The use of TI’s LMCMOS process allows this low supply current and voltage capability. Reduced supply current spikes during output transitions and extremely low reset, trigger and threshold currents also provide low power dissipation advantages with the LMC555.

8.3.2 Various Packages and Compatibility

There are various packages available for use of the LMC555. In addition to the standard package (8-pin SOIC, VSSOP, and PDIP, the LMC555 is also available in a chip-sized package (8-bump DSBGA). The PDIP, SOIC, and VSSOP packages for the LMC555 are pin-for-pin compatible with the 555 series of timers (NE555/SE555/LM555) allowing flexibility in design and unnecessary modifications to PCB schematics and layouts.

8.3.3 Operates in Both Astable and Monostable Mode

The LMC555 can operate in both astable and monostable mode depending on the application requirements.

  • Monostable mode: The LMC555 timer acts as a “one-shot” pulse generator. The pulse begins when the LMC555 timer receives a signal at the trigger input that falls below a 1/3 of the voltage supply. The width of the output pulse is determined by the time constant of an RC network. The output pulse ends when the voltage on the capacitor equals 2/3 of the supply voltage. The output pulse width can be extended or shortened depending on the application by adjusting the R and C values.
  • Astable (free-running) mode: The LMC555 timer can operate as an oscillator and puts out a continuous stream of rectangular pulses having a specified frequency. The frequency of the pulse stream depends on the values of RA, RB, and C.

8.4 Device Functional Modes

8.4.1 Monostable Operation

In this mode of operation, the timer functions as a one-shot (Figure 3). The external capacitor is initially held discharged by internal circuitry. Upon application of a negative trigger pulse of less than 1/3 VS to the Trigger terminal, the flip-flop is set which both releases the short circuit across the capacitor and drives the output high.

LMC555 866904.png Figure 3. Monostable (One-Shot)

The voltage across the capacitor then increases exponentially for a period of tH = 1.1 RAC, which is also the time that the output stays high, at the end of which time the voltage equals 2/3 VS. The comparator then resets the flip-flop which in turn discharges the capacitor and drives the output to its low state. Figure 4 shows the waveforms generated in this mode of operation. Because the charge and the threshold level of the comparator are both directly proportional to supply voltage, the timing internal is independent of supply.

LMC555 866910.png
VCC = 5 V       Top Trace: Input 5 V/Div.

TIME = 0.1 ms/Div.  Middle Trace: Output 5 V/Div.

RA = 9.1 kΩ      Bottom Trace: Capacitor Voltage 2 V/Div.

C = 0.01 µF
Figure 4. Monostable Waveforms

Reset overrides Trigger, which can override threshold. Therefore the trigger pulse must be shorter than the desired tH. The minimum pulse width for the Trigger is 20 ns, and it is 400 ns for the Reset. During the timing cycle when the output is high, the further application of a trigger pulse will not effect the circuit so long as the trigger input is returned high at least 10 µs before the end of the timing interval. However the circuit can be reset during this time by the application of a negative pulse to the reset terminal. The output will then remain in the low state until a trigger pulse is again applied.

When the reset function is not use, it is recommended that it be connected to V+ to avoid any possibility of false triggering. Figure 5 is a nomograph for easy determination of RC values for various time delays.

NOTE

In monstable operation, the trigger should be driven high before the end of timing cycle.

LMC555 866911.png Figure 5. Time Delay

8.4.2 Astable Operation

If the circuit is connected as shown in Figure 6 (Trigger and Threshold terminals connected together) it will trigger itself and free run as a multivibrator. The external capacitor charges through RA + RB and discharges through RB. Thus the duty cycle may be precisely set by the ratio of these two resistors.

LMC555 866905.png Figure 6. Astable (Variable Duty Cycle Oscillator)

In this mode of operation, the capacitor charges and discharges between 1/3 VS and 2/3 VS. As in the triggered mode, the charge and discharge times, and therefore the frequency are independent of the supply voltage.

Figure 7 shows the waveform generated in this mode of operation.

LMC555 866912.png
VCC = 5 V      Top Trace: Output 5 V/Div.

TIME = 20 µs/Div.   Bottom Trace: Capacitor Voltage 1 V/Div.

RA = 3.9 kΩ

RB = 9 kΩ

C = 0.01 µF
Figure 7. Astable Waveforms

The charge time (output high) is given by

Equation 1. t1 = 0.693 (RA + RB)C

And the discharge time (output low) by:

Equation 2. t2 = 0.693 (RB)C

Thus the total period is:

Equation 3. T = t1 + t2 = 0.693 (RA + 2RB)C

The frequency of oscillation is:

Equation 4. LMC555 866924.png

Figure 8 may be used for quick determination of these RC Values. The duty cycle, as a fraction of total period that the output is low, is:

Equation 5. LMC555 866925.gif
LMC555 866913.png Figure 8. Free-Running Frequency