SNAS558M February 2000 – July 2016 LMC555
Standard PCB rules apply to routing the LMC555. The 0.1 µF in parallel with a 1-µF electrolytic capacitor should be as close as possible to the LMC555. The capacitor used for the time delay should also be placed as close to the discharge pin. A ground plane on the bottom layer can be used to provide better noise immunity and signal integrity.
The figure below is the basic layout for various applications.