SNLS309I April   2010  – December 2014 LMH1983


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configurations and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Frame Timing Outputs Timing Requirements
    7. 7.7 Frame Timing Outputs Switching Characteristics
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Control of PLL1
      2. 8.3.2  PLL1 Loop Response Design Equations
      3. 8.3.3  Control of PLL2 and PLL3
      4. 8.3.4  Control of PLL4
      5. 8.3.5  Clock Output Jitter
      6. 8.3.6  Lock Determination
      7. 8.3.7  Lock Time Considerations
      8. 8.3.8  LOR Determination
      9. 8.3.9  Output Driver Adjustments
      10. 8.3.10 TOF1 Alignment
      11. 8.3.11 TOF2 and TOF3 Alignment
        1. TOF3 Initialization Set Up
      12. 8.3.12 TOF4 Alignment
    4. 8.4 Device Functional Modes
      1. 8.4.1 Reference Detection
      2. 8.4.2 User Defined Formats
      3. 8.4.3 Auto Format Detection Codes
      4. 8.4.4 Free-Run, Genlock, and Holdover Modes
    5. 8.5 Programming
      1. 8.5.1 I2C Interface Protocol
      2. 8.5.2 Write Sequence
      3. 8.5.3 Read Sequence
    6. 8.6 Register Map
  9. Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Typical Genlock Timing Generation with NTSC 525i/29.97 High Speed Reference
        1. Design Requirements
          1. VCXO Selection Criteria
          2. Loop Filter Capacitors
        2. Detailed Design Procedure
        3. Application Curves
      2. 9.2.2 A/V Clock Generation with Recognized Clock-based Input Reference
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curve
      3. 9.2.3 A/V Clock Generation Using Free-Run Mode
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

When designing the PCB layout for the LMH1983, it is important to follow these the guidelines:

  • Whenever possible, dedicate an entire layer to each power supply. This will reduce the inductance in the supply plane.
  • Use surface mount components whenever possible.
  • Place bypass capacitors and filter components as close as possible to each power pin.
  • Place the loop filter components, including the buffer amplifier, and VCXO as close as possible to the LMH1983.
  • Do not allow discontinuities in the ground planes – return currents follow the path of least resistance. For high frequency signals this will be the path of least inductance.
  • Make sure to match the trace lengths of all differential traces.
  • Remember that vias have significant inductance — when using a via to connect to a power supply or ground layer, two in parallel will reduce the inductance over a single via.
  • Connect the pad on the bottom of the package to a solid ground connection. This contact is used as a major ground connection as well as providing a thermal conduit which helps to maintain a constant die temperature.
  • See Application Note: AN-1187, Leadless Leadframe Package (LLP) (SNOA401) for more Information on the LLP (WQFN) style package.

11.2 Layout Example

30085164.gifFigure 33. LMH1983 Typical Interface Circuit

An example of a typical application circuit for the LMH1983 is shown in the Figure 33. When performing PCB layout, key areas to consider regarding this circuit are the loop filter – which consists of RS, CS, CP and the LM7711 Operational Amplifier which buffers the loop filter output prior to driving the control voltage input of the VCXO. Care must be taken in the component selection for the loop filter components (see VCXO Selection Criteria and Loop Filter Capacitors). The CLKout outputs are differential LVDS signals and should be treated as differential signals. These signals may be laid out as fully differential lines, in which the characteristic impedance between the two lines is nominally 100 Ω. Alternately, loosely coupled lines may be used, in which case the characteristic impedance of each line should be 50 Ω referenced to GND. In either case, care should be taken to match the lengths of the traces as closely as possible. Trace length mismatches on a differential line will add to the jitter seen on that line. Jitter is also added to the clock outputs if other signals are allowed to interfere with the signal traces. Therefore, to the greatest extent possible, the clock traces should be isolated from other signals. Long parallel runs should also be avoided. In places where a hostile signal must cross a sensitive clock signal, it should be routed such that it crosses as closely as possible to a 90° crossing.

When performing board layouts with the LMH1983, stencil parameters such as aperture area ratio and the fabrication process have a significant impact on paste deposition. Inspection of the stencil prior to placement of the WQFN package is highly recommended to improve board assembly yields. If the via and aperture openings are not carefully monitored, the solder may flow unevenly through the DAP. Stencil parameters for aperture opening and via locations are shown in Figure 34.

LLP_stencil_nopullback_explanation_diagram_snls302.pngFigure 34. No Pullback LLP, Single Row Reference Diagram

Table 14. No Pullback LLP Stencil Aperture Summary for LMH1983

(DIM A mm)
LMH1983 40 SNA40A 0.25 x 0.6 0.5 4.6 x 4.6 0.25 x 0.7 1.0 x 1.0 16 0.2
lmh1983_dap.gifFigure 35. 40-Pin WQFN Stencil Example of Via and Opening Placement

The following PCB layout example is derived from the layout design of the LMH1983 in the SD1983EVK Evaluation Module User's Guide (SNLU001). This graphic and additional layout board description demonstrates both proper routing and solder techniques when designing in this clock generator.

sd1983evk_layout_example.gifFigure 36. LMH1983 Example Layout