8.3.1 Control of PLL1

PLL1 generates a 27 MHz reference that is used as the primary frequency reference for all of the other PLLs in the device. PLL1 has a dual loop architecture with the primary loop locking the external 27 MHz VCXO to a harmonic of the H_IN signal. In addition to this loop, there is a secondary loop that may be used in genlock operations. This second loop compares the phase of the TOF1 output signal from the LMH1983 to the F_IN signal. In order to bring the frame alignment of the output signals into sync with the input reference, the second loop may override the primary loop. Detailed information about controlling this functionality is described in TOF1 Alignment.

To illustrate the dual loop architecture of PLL1, refer to the PLL1 block diagram in Figure 9. The primary loop takes the reference applied to the H_IN input and divides that by R (stored in Registers 0x29 and 0x2A). The dividend is then compared in phase and frequency to the output of the external 27 MHz VCXO divided by N (stored in Registers 0x2B and 0x2C). The PFD (phase frequency detector) then generates output pulses that are integrated via an external loop filter that drives the control voltage of the external VCXO.

Since PLL2, PLL3, and PLL4 all use PLL1 as their input reference, the performance of PLL1 affects the performance of all four clock outputs. The loop filters for the other three PLLs are internal, and the bandwidths are set significantly higher than that of PLL1, so the low frequency jitter characteristics of all four clock outputs are determined by the loop response of PLL1. Accordingly, special attention should be paid to the PLL1's loop bandwidth and damping factor.

8.3.2 PLL1 Loop Response Design Equations

The loop response is primarily determined by the loop filter components and the loop gain. A passive second order loop filter consisting of R_S, C_S, and C_P components can provide sufficient input jitter attenuation for most applications. In some cases, a higher order filter may be used to shape the low frequency response of PLL1 further. Assuming a topology for the loop filter similar to that shown in the Figure 9, the bandwidth of the PLL is determined by:

Under normal operation, several of these parameters are set by the device automatically, for example the charge pump current and the value of 'FB_DIV'. When the input reference format changes, both N and the charge pump current are updated, N is changed to allow for lock to the new reference, and the charge pump current is adjusted to maintain constant loop bandwidth.

It should be noted that this bandwidth calculation is an approximation and does not take into account the effects of the damping factor or the second pole introduced by C_P.

At frequencies far above the –3dB loop bandwidth, the closed-loop frequency response of PLL1 will roll off at about –40dB/decade, which is useful for attenuating input jitter at frequencies above the loop bandwidth. Near the –3dB corner frequency, the roll-off characteristic depends on other factors, such as damping factor and filter order.

To prevent output jitter due to the modulation of the VCXO by the PLL's phase comparison frequency, the bandwidth needs to meet the following criterion:

PLL1's damping factor can be approximated by:

Typically, DF is targeted to be between 1/√2 and 1, which will yield a good trade-off between lock time and reference spur attenuation. DF is related to the phase margin, a measure of the PLL stability.

There is a second parallel capacitor, C_P, which is needed to filter the reference spurs introduced by the PLL. The spurs may modulate the VCXO control voltage, leading to jitter. The following relationship should be used to determine C_P:

The PLL loop gain, K, can be calculated as:

Therefore, Bandwidth and Damping Factor can be expressed in terms of K:

8.3.3 Control of PLL2 and PLL3

PLL2 and PLL3 have the least amount of flexibility of the four PLLs in the LMH1983. They are pre-programmed to run at 148.5 MHz and 148.35 MHz respectively. There is a divide-by-two option available to allow the output to be 74.25 MHz or 74.18 MHz, should these frequencies be required. These two PLLs can also be disabled – disabling PLL2 or PLL3 can save significant amounts of power if that particular clock is not required. Figure 11 shows a simplified functional block diagram of PLL2 and PLL3.

8.3.4 Control of PLL4

Although originally intended to generate only a clock for audio use, PLL4 features much greater versatility. Several registers may be used to configure PLL4 to generate a broad selection of frequencies. The default state for PLL4 is to generate 24.576 MHz (48 kHz x 512) on the output of CLK4 and a 5.996 Hz output from TOF4. This is done by taking CLK1 (27 MHz), and dividing by 75, resulting in a signal of 360 kHz. This frequency is compared to the internal PLL4 VCO, nominally 1.2 GHz, divided by 4096. The VCO frequency is adjusted via register control until the resulting frequency yields 360 kHz. The final VCO frequency is then divided by 12 to generate a 98.304 MHz signal (48 kHz x 2048). Any power of two multiple of 48 kHz can be generated by changing the contents of the PLL4_DIV component of Register 0x34. Note that the divider here is in powers of 2, so the default value of 2 results in the 98.304 MHz signal being divided by 2² or 4. The final CLKout4 frequency is therefore 24.576 MHz. PLL4_DIV is a 4-bit value, so values up to 15 may be programmed, resulting in a divide by 2¹⁵ or 32,768. If audio clocks based on a 44.1 kHz sampling clock are desired, refer to Application Note AN–2108, Generating 44.1 kHz Based Clocks with the LMH1983, (SNLA129) for detailed instructions.

TOF4 has two different operation modes. When the AFS_mode bit (Register 0x09) is set to a 0, then TOF4 is derived by dividing CLKout4 by a value of 2^TOF4_ACLK (Register 0x4A). if the AFS_mode bit is set to 1, then TOF4 is derived from TOF1 — divided by AFS_div (Register 0x49). When AutoFormatDetect is true, then the AFS_div register is read only and is internally set depending upon the format detected.

8.3.5 Clock Output Jitter

Many circuits that require video clocks, such as the embedded Serializers and Deserializers found in FPGAs, are sensitive to jitter. In all real world applications, jitter has a random component, so it is best specified in statistical terms. The SMPTE serial standards (SMPTE 259M, SMPTE 292M and SMPTE 424M) use a frequency domain method of specifying jitter where they refer to the peak-to-peak jitter of a signal after the jitter has been bandpass filtered. Jitter at frequencies below 10 Hz is ignored, and the jitter in a band from 10 Hz to an intermediate frequency (1 kHz for the 270 Mbps standard, 100 kHz for the 1.5 Gbps and 3 Gbps standards) is referred to as timing jitter. Jitter from the intermediate frequency up to 1/10 of the serial rate is referred to as alignment jitter. The limits that the SMPTE standards place are peak-to-peak limits, but especially at the higher rates, random processes have a significant impact, and it is not possible to consider peak-to-peak jitter without a corresponding confidence level. The methodology used to specify the jitter on the LMH1983 decomposes the jitter into a deterministic component (t_DJ) plus a random component (t_RJ). This is the methodology used by the jitter analysis tools supported on high bandwidth oscilloscopes and timing analysis tools from major instrumentation manufacturers.

To convert between RMS jitter and peak-to-peak jitter, the Bit Error Rate (BER) must be specified. Since jitter is a random event, without a known BER, the peak-to-peak jitter will be dependent upon the observation time and can be arbitrarily large. The equation that links peak-to-peak jitter to RMS jitter is:

where α is determined by the BER according to the equation:

The erfc (error function) can be found in several mathematics references and is also a function in both Excel and MATLAB. A fairly common BER used for these calculations is 10^-12, which yields a value of α = 14.

Another common method for evaluating the jitter of a clock output is to look at the phase noise as a function of frequency. Plots showing the phase noise for each of the four CLKout outputs can be found in Figure 1 through Figure 8.

8.3.6 Lock Determination

There are four bits in Register 0x02 that indicate the lock status of the four PLLs. Lock determination for PLL1 can be controlled through two registers: LockStepSize (Register 0x2D) and Loss of Lock Threshold (Register 0x1C). The LockStepSize register sets the amount of variation that is permitted on the VC_LPF pin while still considering the device to be locked. If the reference to the LMH1983 has a large amount of jitter, then the device may be unable to declare lock because the LockStepSize is set too low. The second register, the Loss of Lock Threshold register, controls the lock state declaration of PLL1. This register sets a number of cycles on the H_IN input that must be seen before loss of lock is declared. For some reference signals, there can be several missing H_IN pulses during vertical refresh. Therefore, it is suggested that this register be loaded with a value greater than six (Loss of Lock Threshold > 6). Pin 11, NO_LOCK, gives the lock status of the LMH1983. Note that the status of the NO_LOCK pin can also be read from Register 0x01, and it is a logical OR of the four individual NO_LOCK status bits of the four PLLs. The NO_LOCK status pin is masked by the bits in the PLL Lock mask (Register 0x1D), and the status is also masked if an individual PLL is powered down.

8.3.7 Lock Time Considerations

The lock time of the LMH1983 is dominated by the lock time of PLL1. The other PLLs have much higher loop bandwidths, and as a result, they lock more quickly than PLL1 does. Therefore, lock time considerations mainly rely on PLL1. The lock time for a PLL is dependent upon the loop bandwidth (see Equation 1). A small loop bandwidth typically increases the time required to achieve lock. To counter this issue, the LMH1983 also allows a Fastlock mode. In this mode, the bandwidth is increased by increasing the charge pump current when the loop is unlocked. Then, at a time programmed by the user after lock is declared, I_CP1 is throttled back to drop the bandwidth to the desired set point. The result is both fast lock time and very low residual jitter.

Another factor when considering lock time is whether 'drift lock' has been enabled or not (see TOF1 Alignment). If drift lock is enabled and there is a significant difference in the phase of TOF1 relative to the F_IN signal, the VCXO is slewed to ramp the clock rate up or down until the two framing signals are brought into alignment. It is possible that this process may take a long time (tens of seconds).

Aside from the time required for the PLL to lock, there is a circuit that determines how to set the NO_LOCK output pin. The LMH1983 PLL operates by adjusting the voltage that is applied to the VCXO control pin to lock the VCXO to a harmonic of the incoming reference. When the device is not locked, the PLL pulls the VCXO control voltage to one extreme of its range to slew the voltage into lock. Once the phase differences between the VCXO and the reference are small, the device begins to nudge the control voltage back and forth to maintain the phase difference. An adjustment might be necessary either due to VCXO drift or due to jitter on the reference. To determine the status of NO_LOCK, the LMH1983 establishes a window to view the amount of adjustment that is required over a period of time. Two parameters are set via register control to determine NO_LOCK status. LockStepSize (Register 0x2D) sets the amount of time in which to observe the signal, and Loss of Lock Threshold (Register 0x1C) sets the amount of variation in the control voltage that can be seen over this time frame while still considering the device to be locked.

To minimize the amount of time necessary to assert lock, load LockStepSize (Register 0x2D) with a value of 0x01 and the Loss of Lock Threshold (Register 0x1C) with a value of 0x1F. The effect of this change can be seen in Figure 13:

8.3.8 LOR Determination

When the PLL is not locked, there is an internal counter that counts the number of 27 MHz clock pulses between consecutive HSync pulses divide-by-two. This counter saturates at 0x7FFF (or 32767 decimal). Once this counter saturates, LOR is declared. Given this is a divide-by-two counter, the time to declare LOR is: (2 x 32767) / (27E6) = 2.4 ms. On the other hand, when the PLL is locked and there are missing HSync pulses, LOR is set when the internal counter is greater than the following: (Number of 27 MHz clocks in one Hsync pulse + 3) x (LOR_THRES + 1).

8.3.9 Output Driver Adjustments

The LVDS output drivers can be adjusted via the I²C interface to change the differential output voltage swing, the common mode voltage, and the amount of pre-emphasis applied to the LVDS output:

• Register 0x3A, Bit 7 turns on the pre-emphasis, which may be used to extend the reach between the LMH1983 and the load. It is recommended that the trace length is kept short, as longer traces have more opportunity to couple with hostile signals and degrade jitter performance.
• The differential output swing of the CLKout pins is adjusted through Register 0x3A, Bits [6:4]. A larger value loaded into Bits [6:4] correspond to an increase in the output swing.
• The common mode output voltage can be adjusted via Register 0x3A, Bits [3:0].

8.3.10 TOF1 Alignment

Each of the four clock outputs has a corresponding Top Of Frame (TOF) output signal. The LMH1983 is programmed with a video format for each of the three video clocks (CLKout 1-3), and the TOF signal provides a digital indication when the start of a new frame occurs for that particular format. As an example, if PLL1 is programmed with a video format corresponding to NTSC, CLK1 is 27 MHz, and TOF1 outputs a pulse once per frame, or once every 900,900 clock cycles. In its default state, the LMH1983 detects the input reference format and programs this format as the output format for CLKout1. Therefore, if the input reference is an NTSC reference, then TOF1 will default to a 29.97 Hz signal.

If the H_IN, V_IN, and F_IN inputs to the LMH1983 are coming from the LMH1981 Sync Separator, then the rising edge of the F_IN input will come in the middle of a line (between H_IN pulses). The TOF pulse, if aligned, will be a pulse with a width of 1 x H period and transitions aligned with the leading edges of the H_IN pulses. When set for zero offset, the TOF pulse will be high during the H period where the F_IN input transitions, as seen in Figure 14.

The alignment between the incoming F_IN and the TOF1 output may be controlled in a number of ways. There are three different alignment modes in which TOF1 may operate as selected via Register 0x11:

1. 11'b (default): PLL1 never attempts to align.
2. 10'b: PLL1 always forces alignment to F_IN.
3. 00'b: Automatically force alignment to F_IN when they are misaligned.

Misalignment can be defined by the user via Register 0x15. In Register 0x15, a time window is defined to specify the amount of mismatch permitted between F_IN and TOF1 while still considering them to be aligned. If the input reference signal has a significant amount of low frequency jitter or wander, it may be possible for the relative alignment between TOF1 and F_IN to vary over time. Selecting "Always Align" mode may lead to undesirable timing jumps on the output of CLKout1/TOF1.

Once the device decides that it needs to align TOF1 and F_IN, there are two ways that it can be done. Crash lock involves simply resetting the counter that keeps track of where the TOF1 output transition happens, resulting in an instantaneous shift of TOF1 to align with F_IN. Drift lock involves using the second loop in PLL1 and skewing the VCXO to make the frequency of CLKout1 either speed up or slow down. The VCXO skewing slowly pulls TOF1 and F_IN into alignment. If a new reference is applied that is not in alignment with TOF1, but the output is currently in use, it may be better to slew TOF1 into alignment rather than to cause a major disruption in the timing with a crash lock. The LMH1983 allows the user to select either crash lock or drift lock, controllable via Register 0x11. The option of crash lock or drift lock is available when the difference in phase is small (Output < 2^LOA_window x 27 MHz Clock) and when the difference in phase is large (Output > 2^LOA_window x 27 MHz Clock). Furthermore, if the difference is large, the user can tell the device to achieve alignment either by advancing or retarding the phase of PLL1. Note that if the difference in alignment is large, achieving alignment via drift lock may take a very long time (tens of seconds), during which the output clock will not be phase locked to the input H_IN.

8.3.11 TOF2 and TOF3 Alignment

Similar to TOF1, CLKout2 and CLKout3 have associated video formats. The format is determined by programming Register 0x07 and 0x08, respectively. Once the format is programmed and the TOF outputs are enabled, a TOF pulse is generated at the appropriate rate for each of the outputs. There are four different alignment modes that may be selected for TOF2 and TOF3:

TOF2 and TOF3 are generally aligned with TOF1. The alignment status bit will only be set if the frame rates are the same as one another. Another option for alignment is via software, where the TOFX_INIT bit is set. For example, the LSB of Register 0x12 is the TOF2_INIT bit. Writing a 1 to this bit while also setting TOF2 alignment mode to anything other than 3 (Never Align) will cause TOF2 to reset its phase immediately. Note that this bit is a self-clearing bit, so it will always return a zero.

8.3.12 TOF4 Alignment

CLKout4 of the LMH1983 is most often used to generate an audio clock. The default base audio clock rate is 48 kHz, and this sample clock is synchronous in phase with the video frame only once every 5 frames for 29.97 and 30 Hz frame rate standards, or once every ten frames for 60 Hz and 59.94 Hz systems. The LMH1983 can generate a TOF4 pulse that occurs at this rate, allowing audio frames to be synchronized with the video frames.

TOF4 may be aligned either to TOF1 or to the F_IN input. Additionally, there is an external INIT input that can be used to set TOF4 alignment.

8.4.1 Reference Detection

The device uses Auto Format Detect as the default mode, as the device determines the reference format among those shown in Auto Format Detection Codes, and initiates the internal configurations accordingly. There are 31 pre-defined formats plus one format that the user can define. The device recognizes a format by measuring the H_IN input frequency and looking at the V_IN and F_IN inputs. The device then determines if the reference input format is an interlaced or progressive input. For some formats such as a 10 MHz or 27 MHz Hsync reference, if H_IN and V_IN create a spurious input, the device will not properly recognize the reference input and will not lock properly to the reference. Because of this, if H_IN has one of these 'special' signals on it, V_IN and F_IN should be muted.

8.4.2 User Defined Formats

There are several registers in the LMH1983 that are loaded automatically based on the format of the reference that is detected. The LMH1983 allows the user to define a non-standard format and a corresponding set of values to load into the appropriate registers if that format is detected. In order to identify the format, the LMH1983 measures the frequency of the Hsync input, counts the number of lines per frame in the format, and detects if the particular format is interlaced or progressive. The Hsync frequency is measured by counting the number of 27 MHz clock edges that occur in a period of time equal to 20 horizontal sync times. To implement a user defined format, the following registers are configured:

• The minimum and maximum permissible count must be set, thereby establishing a window of frequency for Hsync. Registers 0x51 and 0x52 define the 16-bit value for the low end of the frequency range, while Registers 0x53 and 0x54 define the high end of the frequency range.
• Registers 0x5A and 0x5B define the number of lines per frame for the format.
• Register 0x5D, Bit 4 indicates whether the user defined format is interlaced or not.
• Register 0x5D, Bit 7 enables the detection of a user-defined format.
• Once the user-defined format is detected, the contents of Registers 0x55 through 0x59 configure PLL1 to lock to 27MHz, which is then used as the reference for PLL2, PLL3, and PLL4.

Table 2. Supported Formats Lookup Table (LUT)

FORMAT	INPUT TIMING / PLL1 PARAMETERS				OUTPUT TIMING (OUT1–4) PARAMETERS
	Reference Divider	Feedback Divider	Phase Detector (PD) Freq. (kHz)	PD Periods per Frame Counter	PLL#	PLL Clock Freq. (MHz)	Total Clocks per Line Counter	Total Lines per Frame Counter	Frame Rate (Hz)
NTSC, 525i	1	1716	15.7343	525	1	27.0	1716	525	29.97
					2	148.5	9438
PAL, 625i	1	1728	15.625	625	1	27.0	1728	625	25
					2	148.5	9504
525p	1	858	31.4685	525	1	27.0	858	525	59.94
					2	148.5	4719
625p	1	864	31.25	625	1	27.0	864	625	50
					2	148.5	4752
720p/60	1	600	45.0	750	2	148.5	3300	750	60
720p/59.94	5	3003	8.99101	150	3	148.35	3300	750	59.94
720p/50	1	720	37.5	750	2	148.5	3960	750	50
720p/30	1	1200	22.5	750	2	148.5	6600	750	30
720p/29.97	5	6006	4.49550	150	3	148.35	6600	750	29.97
720p/25	1	1440	18.75	750	2	148.5	7920	750	25
720p/24	1	1500	18.0	750	2	148.5	8250	750	24
720p/23.98	2	3003	8.99101	375	3	148.35	8250	750	23.98
1080p/60	1	400	67.5	1125	2	148.5	2200	1125	60
1080p/59.94	5	2002	13.48651	225	3	148.35	2200	1125	59.94
1080p/50	1	480	56.25	1125	2	148.5	2640	1125	50
1080p(psF)/30	1	800	33.75	1125	2	148.5	4400	1125	30
1080p(psF)/29.97	5	4004	6.74326	225	3	148.35	4400	1125	29.97
1080p(psF)/25	1	960	28.125	1125	2	148.5	5280	1125	25
1080p(psF)/24	1	1000	27.0	1125	2	148.5	5500	1125	24
1080p(psF)/23.98	1	1001	26.9730	1125	3	148.35	5500	1125	23.98
1080i/60	1	800	33.75	1125	2	148.5	4400	1125	30
1080i/59.94	5	4004	6.74326	225	3	148.35	4400	1125	29.97
1080i/50	1	960	28.125	1125	2	148.5	5280	1125	25
48 kHz word clock	2	1125	24.0	1	4	98.304	2048	1	48000
96 kHz word clock	4	1125	24.0	1	4	98.304	1024	1	96000
27 MHz osc clk	1000	1000	27.000	1	Input only
10 MHz GPS osc clk	600	1620	16.6666	1	Input only

8.4.3 Auto Format Detection Codes

The Auto Format Detection Codes apply to Registers 0x07 (Output Mode – PLL2 Format), 0x08 (Output Mode – PLL3 Format), and 0x20 (Input Format).

8.4.4 Free-Run, Genlock, and Holdover Modes

The LMH1983 primary PLL can operate in three different modes, selected via Register 0x05. These modes are Free-run, Genlock, and Holdover Mode:

• Free-run mode: H_IN, V_IN, and F_IN are not used, and the VCXO control voltage is set by the contents of Registers 0x18 and 0x19. By writing to these registers, the VCXO voltage can be trimmed up or down. The slave PLLs will remain locked to the primary PLL.
• Genlock mode: The VCXO control voltage is actively controlled to maintain lock between H_IN and the VCXO output frequency. In addition, there is a second PLL loop that may take over to assert a lock between TOF1 and F_IN. See TOF1 Alignment for more details.
• Holdover mode: In the event that the reference is lost, there is an A/D — D/A pair that is able to take over for the PLL control loop and hold the VCXO control voltage constant. For this to work properly, the device must realize that it has lost its reference shortly after the reference is actually lost. Some sync separators, when the analog input is lost, will output random pulses from the H, V, and F outputs. This can confuse the device. Therefore if Holdover mode is to be used in conjunction with an analog sync separator, it is best to gate the H, V, and F signals with a signal that indicates if there is a valid reference input.

8.5.1 I²C Interface Protocol

The protocol of the I²C interface begins with the start pulse, followed by a byte which consists of a seven-bit slave device address and a Read/Write bit as an LSB. The default address of the LMH1983 for write sequences is 0xCC (11001100'b) and for read sequences is 0xCD (11001101'b). The base address can be changed with the ADDR pin. When ADDR is left open, the base address is 0x66 (which, when left shifted for a write sequence becomes 0xCC). When ADDR is connected to GND, the base address is 0x65, and when ADDR is connected to V_DD, the base address is 0x67.

Please note: The I2C interface of the LMH1983 requires the 27 MHz VCXO clock input to be running in order to read I2C data packets into the 27 MHz clock domain. If the 27 MHz clock is not running, the I2C interface should still respond (ACK), but Write commands may be ignored and Read commands may return invalid data.

8.5.2 Write Sequence

The write sequence begins with a start condition, which consists of the master pulling SDA low while SCL is high. The slave address is sent next. The slave address is a seven-bit address followed by the Read/Write bit (Read = 1'b and Write = 0'b). For the default base address of 0x66 (1100110'b), the 0 is appended to the end, and the net address is 0xCC. Each byte sent after the address is followed by an ACK bit. When SCL is high, the master will release the SDA line, and the slave pulls SDA low to acknowledge. Once the device address has been sent, the next byte sent is the register address. Following the register address and the ACK, the data byte is sent. When more than one data byte is sent, the register address is automatically incremented so that the data is written into the next address location. The Write Sequence Timing Diagram is shown in Figure 19. Note that there is an ACK bit following each data byte.

8.5.3 Read Sequence

Read sequences consist of two I²C transfers. The first is the address access transfer, which consists of a write sequence that transfers only the address to be accessed. The second is the data read transfer which starts at the address indicated in the first transfer and increments to the next address, continuing to read addresses until a stop condition is encountered. The timing diagram of the address access transfer is shown in Figure 20. A read sequence begins with a start pulse, the slave device address including the Read/Write bit (Read = 1'b and Write = 0'b), and then its ACK bit. The next byte is the address to be read, followed by the ACK bit and the stop bit to indicate the end of the address access transfer. The subsequent read data transfer shown consists of the start pulse, the slave device address including the Read/Write bit (this time a R/W Bit = 1'b, indicating that the data is to be read) and the ACK bit. The next byte is the data read from the initial access address. After each data byte is read, the address is incremented, thereby allowing the next byte of data to be read from the subsequent address of the device. Each byte is separated from the previous byte by an ACK bit, and the end of the read sequence is indicated with a STOP bit. The timing diagram for a read data transfer is shown in Figure 21 for additional timing details.

The following table provides details on the device's configuration registers. Default value for fields that are seven bits or less are expressed in binary, and default values for fields that are 8 bits (Byte) are expressed in hex. Do not write to Reserved (RSVD) fields.