SNAS688C Februray   2017  – May 2018 LMK04832

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagram
    8. 6.8 Typical Characteristics – Clock Output AC Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Charge Pump Current Specification Definitions
      1. 7.1.1 Charge Pump Output Current Magnitude Variation vs Charge Pump Output Voltage
      2. 7.1.2 Charge Pump Sink Current vs Charge Pump Output Source Current Mismatch
      3. 7.1.3 Charge Pump Output Current Magnitude Variation vs Ambient Temperature
    2. 7.2 Differential Voltage Measurement Terminology
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1  Differences to LMK0482x
      2. 8.1.2  Jitter Cleaning
      3. 8.1.3  JEDEC JESD204B Support
      4. 8.1.4  Clock Inputs
        1. 8.1.4.1 Three Redundant PLL1 Reference Inputs
        2. 8.1.4.2 PLL2 Reference Inputs
        3. 8.1.4.3 Clock Distribution Reference Input
      5. 8.1.5  VCXO Buffered Output
      6. 8.1.6  Frequency Holdover
      7. 8.1.7  Internal VCOs
      8. 8.1.8  External VCO Mode
      9. 8.1.9  Clock Distribution
        1. 8.1.9.1 Clock Divider
        2. 8.1.9.2 High Performance Divider Bypass Mode
        3. 8.1.9.3 SYSREF Clock Divider
        4. 8.1.9.4 Device Clock Delay
        5. 8.1.9.5 Dynamic Digital Delay
        6. 8.1.9.6 SYSREF Delay: Global and Local
        7. 8.1.9.7 Programmable Output Formats
        8. 8.1.9.8 Clock Output Synchronization
      10. 8.1.10 0-Delay
      11. 8.1.11 Status Pins
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Synchronizing PLL R Dividers
        1. 8.3.1.1 PLL1 R Divider Synchronization
        2. 8.3.1.2 PLL2 R Divider Synchronization
      2. 8.3.2 SYNC/SYSREF
      3. 8.3.3 JEDEC JESD204B
        1. 8.3.3.1 How to Enable SYSREF
          1. 8.3.3.1.1 Setup of SYSREF Example
          2. 8.3.3.1.2 SYSREF_CLR
        2. 8.3.3.2 SYSREF Modes
          1. 8.3.3.2.1 SYSREF Pulser
          2. 8.3.3.2.2 Continuous SYSREF
          3. 8.3.3.2.3 SYSREF Request
      4. 8.3.4 Digital Delay
        1. 8.3.4.1 Fixed Digital Delay
          1. 8.3.4.1.1 Fixed Digital Delay Example
        2. 8.3.4.2 Dynamic Digital Delay
        3. 8.3.4.3 Single and Multiple Dynamic Digital Delay Example
      5. 8.3.5 SYSREF to Device Clock Alignment
      6. 8.3.6 Input Clock Switching
        1. 8.3.6.1 Input Clock Switching - Manual Mode
        2. 8.3.6.2 Input Clock Switching - Pin Select Mode
        3. 8.3.6.3 Input Clock Switching - Automatic Mode
      7. 8.3.7 Digital Lock Detect
        1. 8.3.7.1 Calculating Digital Lock Detect Frequency Accuracy
      8. 8.3.8 Holdover
        1. 8.3.8.1 Enable Holdover
          1. 8.3.8.1.1 Fixed (Manual) CPout1 Holdover Mode
          2. 8.3.8.1.2 Tracked CPout1 Holdover Mode
        2. 8.3.8.2 During Holdover
        3. 8.3.8.3 Exiting Holdover
        4. 8.3.8.4 Holdover Frequency Accuracy and DAC Performance
      9. 8.3.9 PLL2 Loop Filter
    4. 8.4 Device Functional Modes
      1. 8.4.1 DUAL PLL
        1. 8.4.1.1 Dual Loop
        2. 8.4.1.2 Dual Loop With Cascaded 0-Delay
        3. 8.4.1.3 Dual Loop With Nested 0-Delay
      2. 8.4.2 Single PLL
        1. 8.4.2.1 PLL2 Single Loop
        2. 8.4.2.2 PLL2 With External VCO
      3. 8.4.3 Distribution Mode
    5. 8.5 Programming
      1. 8.5.1 Recommended Programming Sequence
    6. 8.6 Register Maps
      1. 8.6.1 Register Map for Device Programming
      2. 8.6.2 Device Register Descriptions
        1. 8.6.2.1 System Functions
          1. 8.6.2.1.1 RESET, SPI_3WIRE_DIS
          2. 8.6.2.1.2 POWERDOWN
          3. 8.6.2.1.3 ID_DEVICE_TYPE
          4. 8.6.2.1.4 ID_PROD
          5. 8.6.2.1.5 ID_MASKREV
          6. 8.6.2.1.6 ID_VNDR
        2. 8.6.2.2 (0x100 - 0x138) Device Clock and SYSREF Clock Output Controls
          1. 8.6.2.2.1 DCLKX_Y_DIV
          2. 8.6.2.2.2 DCLKX_Y_DDLY
          3. 8.6.2.2.3 CLKoutX_Y_PD, CLKoutX_Y_ODL, CLKoutX_Y_IDL, DCLKX_Y_DDLY_PD, DCLKX_Y_DDLY[9:8], DCLKX_Y_DIV[9:8]
          4. 8.6.2.2.4 CLKoutX_SRC_MUX, CLKoutX_Y_PD, DCLKX_Y_BYP, DCLKX_Y_DCC, DCLKX_Y_POL, DCLKX_Y_HS
          5. 8.6.2.2.5 CLKoutY_SRC_MUX, SCLKX_Y_PD, SCLKX_Y_DIS_MODE, SCLKX_Y_POL, SCLKX_Y_HS
          6. 8.6.2.2.6 SCLKX_Y_ADLY_EN, SCLKX_Y_ADLY
          7. 8.6.2.2.7 SCLKX_Y_DDLY
          8. 8.6.2.2.8 CLKoutY_FMT, CLKoutX_FMT
        3. 8.6.2.3 SYSREF, SYNC, and Device Config
          1. 8.6.2.3.1  VCO_MUX, OSCout_MUX, OSCout_FMT
          2. 8.6.2.3.2  SYSREF_REQ_EN, SYNC_BYPASS, SYSREF_MUX
          3. 8.6.2.3.3  SYSREF_DIV
          4. 8.6.2.3.4  SYSREF_DDLY
          5. 8.6.2.3.5  SYSREF_PULSE_CNT
          6. 8.6.2.3.6  PLL2_RCLK_MUX, PLL2_NCLK_MUX, PLL1_NCLK_MUX, FB_MUX, FB_MUX_EN
          7. 8.6.2.3.7  PLL1_PD, VCO_LDO_PD, VCO_PD, OSCin_PD, SYSREF_GBL_PD, SYSREF_PD, SYSREF_DDLY_PD, SYSREF_PLSR_PD
          8. 8.6.2.3.8  DDLYdSYSREF_EN, DDLYdX_EN
          9. 8.6.2.3.9  DDLYd_STEP_CNT
          10. 8.6.2.3.10 SYSREF_CLR, SYNC_1SHOT_EN, SYNC_POL, SYNC_EN, SYNC_PLL2_DLD, SYNC_PLL1_DLD, SYNC_MODE
          11. 8.6.2.3.11 SYNC_DISSYSREF, SYNC_DISX
          12. 8.6.2.3.12 PLL1R_SYNC_EN, PLL1R_SYNC_SRC, PLL2R_SYNC_EN
        4. 8.6.2.4 (0x146 - 0x149) CLKin Control
          1. 8.6.2.4.1 CLKin_SEL_PIN_EN, CLKin_SEL_PIN_POL, CLKin2_EN, CLKin1_EN, CLKin0_EN, CLKin2_TYPE, CLKin1_TYPE, CLKin0_TYPE
          2. 8.6.2.4.2 CLKin_SEL_AUTO_REVERT_EN, CLKin_SEL_AUTO_EN, CLKin_SEL_MANUAL, CLKin1_DEMUX, CLKin0_DEMUX
          3. 8.6.2.4.3 CLKin_SEL0_MUX, CLKin_SEL0_TYPE
          4. 8.6.2.4.4 SDIO_RDBK_TYPE, CLKin_SEL1_MUX, CLKin_SEL1_TYPE
        5. 8.6.2.5 RESET_MUX, RESET_TYPE
        6. 8.6.2.6 (0x14B - 0x152) Holdover
          1. 8.6.2.6.1 LOS_TIMEOUT, LOS_EN, TRACK_EN, HOLDOVER_FORCE, MAN_DAC_EN, MAN_DAC[9:8]
          2. 8.6.2.6.2 MAN_DAC
          3. 8.6.2.6.3 DAC_TRIP_LOW
          4. 8.6.2.6.4 DAC_CLK_MULT, DAC_TRIP_HIGH
          5. 8.6.2.6.5 DAC_CLK_CNTR
          6. 8.6.2.6.6 CLKin_OVERRIDE, HOLDOVER_EXIT_MODE, HOLDOVER_PLL1_DET, LOS_EXTERNAL_INPUT, HOLDOVER_VTUNE_DET, CLKin_SWITCH_CP_TRI, HOLDOVER_EN
          7. 8.6.2.6.7 HOLDOVER_DLD_CNT
        7. 8.6.2.7 (0x153 - 0x15F) PLL1 Configuration
          1. 8.6.2.7.1 CLKin0_R
          2. 8.6.2.7.2 CLKin1_R
          3. 8.6.2.7.3 CLKin2_R
          4. 8.6.2.7.4 PLL1_N
          5. 8.6.2.7.5 PLL1_WND_SIZE, PLL1_CP_TRI, PLL1_CP_POL, PLL1_CP_GAIN
          6. 8.6.2.7.6 PLL1_DLD_CNT
          7. 8.6.2.7.7 HOLDOVER_EXIT_NADJ
          8. 8.6.2.7.8 PLL1_LD_MUX, PLL1_LD_TYPE
        8. 8.6.2.8 (0x160 - 0x16E) PLL2 Configuration
          1. 8.6.2.8.1 PLL2_R
          2. 8.6.2.8.2 PLL2_P, OSCin_FREQ, PLL2_REF_2X_EN
          3. 8.6.2.8.3 PLL2_N_CAL
          4. 8.6.2.8.4 PLL2_N
          5. 8.6.2.8.5 PLL2_WND_SIZE, PLL2_CP_GAIN, PLL2_CP_POL, PLL2_CP_TRI
          6. 8.6.2.8.6 PLL2_DLD_CNT
          7. 8.6.2.8.7 PLL2_LD_MUX, PLL2_LD_TYPE
        9. 8.6.2.9 (0x16F - 0x555) Misc Registers
          1. 8.6.2.9.1 PLL2_PRE_PD, PLL2_PD
          2. 8.6.2.9.2 PLL1R_RST
          3. 8.6.2.9.3 CLR_PLL1_LD_LOST, CLR_PLL2_LD_LOST
          4. 8.6.2.9.4 RB_PLL1_LD_LOST, RB_PLL1_LD, RB_PLL2_LD_LOST, RB_PLL2_LD
          5. 8.6.2.9.5 RB_DAC_VALUE (MSB), RB_CLKinX_SEL, RB_CLKinX_LOS
          6. 8.6.2.9.6 RB_DAC_VALUE
          7. 8.6.2.9.7 RB_HOLDOVER
          8. 8.6.2.9.8 SPI_LOCK
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Digital Lock Detect Frequency Accuracy
        1. 9.1.1.1 Minimum Lock Time Calculation Example
      2. 9.1.2 Driving CLKin AND OSCin Inputs
        1. 9.1.2.1 Driving CLKin and OSCin PINS With a Differential Source
        2. 9.1.2.2 Driving CLKin Pins With a Single-Ended Source
      3. 9.1.3 OSCin Doubler for Best Phase Noise Performance
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Device Selection
          1. 9.2.2.1.1 Clock Architect
        2. 9.2.2.2 Device Configuration and Simulation
        3. 9.2.2.3 Device Programming
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
      1. 9.3.1 Pin Connection Recommendations
  10. 10Power Supply Recommendations
    1. 10.1 Current Consumption
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Thermal Management
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Clock Architect
        2. 12.1.1.2 PLLatinum Sim
        3. 12.1.1.3 TICS Pro
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.6.1 Register Map for Device Programming

Table 5 provides the register map for device programming. Any register can be read from the same data address it is written to.

Table 5. LMK04832 Register Map

ADDRESS
[14:0]		 DATA[7:0]
23:8 7 6 5 4 3 2 1 0
0x000 RESET 0 0 SPI_3WIRE
_DIS		 0 0 0 0
0x002 0 0 0 0 0 0 0 POWER
DOWN
0x003 ID_DEVICE_TYPE
0x004 ID_PROD[15:8]
0x005 ID_PROD[7:0]
0x006 ID_MASKREV
0x00C ID_VNDR[15:8]
0x00D ID_VNDR[7:0]
0x100 DCLK0_1_DIV[7:0]
0x101 DCLK0_1_DDLY[7:0]
0x102 CLKout0_1_PD CLKout0_1_ODL CLKout0_1_IDL DCLK0_1_DDLY_PD DCLK0_1_DDLY[9:8] DCLK0_1_DIV[9:8]
0x103 0 1 CLKout0_SRC_MUX DCLK0_1_PD DCLK0_1_BYP DCLK0_1_DCC DCLK0_1_POL DCLK0_1_HS
0x104 0 0 CLKout1_SRC_MUX SCLK0_1_PD SCLK0_1_DIS_MODE SCLK0_1_POL SCLK0_1_HS
0x105 0 0 SCLK0_1_ADLY_EN SCLK0_1_ADLY
0x106 0 0 0 0 SCLK0_1_DDLY
0x107 CLKout1_FMT CLKout0_FMT
0x108 DCLK2_3_DIV[7:0]
0x109 DCLK2_3_DDLY[7:0]
0x10A CLKout2_3_PD CLKout2_3_ODL CLKout2_3_IDL DCLK2_3_DDLY_PD DCLK2_3_DDLY[9:8] DCLK2_3_DIV[9:8]
0x10B 0 1 CLKout2_SRC_MUX DCLK2_3_PD DCLK2_3_BYP DCLK2_3_DCC DCLK2_3_POL DCLK2_3_HS
0x10C 0 0 CLKout3_SRC_MUX SCLK2_3_PD SCLK2_3_DIS_MODE SCLK2_3_POL SCLK2_3_HS
0x10D 0 0 SCLK2_3_ADLY_EN SCLK2_3_ADLY
0x10E 0 0 0 0 SCLK2_3_DDLY
0x10F CLKout3_FMT CLKout2_FMT
0x110 DCLK4_5_DIV[7:0]
0x111 DCLK4_5_DDLY[7:0]
0x112 CLKout4_5_PD CLKout4_5_ODL CLKout4_5_IDL DCLK4_5_DDLY_PD DCLK4_5_DDLY[9:8] DCLK4_5_DIV[9:8]
0x113 0 1 CLKout4_SRC_MUX DCLK4_5_PD DCLK4_5_BYP DCLK4_5_DCC DCLK4_5_POL DCLK4_5_HS
0x114 0 0 CLKout5_SRC_MUX SCLK4_5_PD SCLK4_5_DIS_MODE SCLK4_5_POL SCLK4_5_HS
0x115 0 0 SCLK4_5_ADLY_EN SCLK4_5_ADLY
0x116 0 0 0 0 SCLK4_5_DDLY
0x117 CLKout5_FMT CLKout4_FMT
0x118 DCLK6_7_DIV[7:0]
0x119 DCLK6_7_DDLY[7:0]
0x11A CLKout6_7_PD CLKout6_7_ODL CLKout6_7_IDL DCLK6_7_DDLY_PD DCLK6_7_DDLY[9:8] DCLK6_7_DIV[9:8]
0x11B 0 1 CLKout6_SRC_MUX DCLK6_7_PD DCLK6_7_BYP DCLK6_7_DCC DCLK6_7_POL DCLK6_7_HS
0x11C 0 0 CLKout7_SRC_MUX SCLK6_7_PD SCLK6_7_DIS_MODE SCLK6_7_POL SCLK6_7_HS
0x11D 0 0 SCLK6_7_ADLY_EN SCLK6_7_ADLY
0x11E 0 0 0 0 SCLK6_7_DDLY
0x11F CLKout7_FMT CLKout6_FMT
0x120 DCLK8_9_DIV[7:0]
0x121 DCLK8_9_DDLY[7:0]
0x122 CLKout8_9_PD CLKout8_9_ODL CLKout8_9_IDL DCLK8_9_DDLY_PD DCLK8_9_DDLY[9:8] DCLK8_9_DIV[9:8]
0x123 0 1 CLKout8_SRC_MUX DCLK8_9_PD DCLK8_9_BYP DCLK8_9_DCC DCLK8_9_POL DCLK8_9_HS
0x124 0 0 CLKout9_SRC_MUX SCLK8_9_PD SCLK8_9_DIS_MODE SCLK8_9_POL SCLK8_9_HS
0x125 0 0 SCLK8_9_ADLY_EN SCLK8_9_ADLY
0x126 0 0 0 0 SCLK8_9_DDLY
0x127 CLKout9_FMT CLKout8_FMT
0x128 DCLK10_11_DIV[7:0]
0x129 DCLK10_11_DDLY[7:0]
0x12A CLKout10_11_PD CLKout10_11_ODL CLKout10_11_IDL DCLK10_11_DDLY_PD DCLK10_11_DDLY[9:8] DCLK10_11_DIV[9:8]
0x12B 0 1 CLKout10_SRC_MUX DCLK10_11_PD DCLK10_11_BYP DCLK10_11_DCC DCLK10_11_POL DCLK10_11_HS
0x12C 0 0 CLKout11_SRC_MUX SCLK10_11_PD SCLK10_11_DIS_MODE SCLK10_11_POL SCLK10_11_HS
0x12D 0 0 SCLK10_11_ADLY_EN SCLK10_11_ADLY
0x12E 0 0 0 0 SCLK10_11_DDLY
0x12F CLKout11_FMT CLKout10_FMT
0x130 DCLK12_13_DIV[7:0]
0x131 DCLK12_13_DDLY[7:0]
0x132 CLKout12_13_PD CLKout12_13_ODL CLKout12_13_IDL DCLK12_13_DDLY_PD DCLK12_13_DDLY[9:8] DCLK12_13_DIV[9:8]
0x133 0 1 CLKout12_SRC_MUX DCLK12_13_PD DCLK12_13_BYP DCLK12_13_DCC DCLK12_13_POL DCLK12_13_HS
0x134 0 0 CLKout13_SRC_MUX SCLK12_13_PD SCLK12_13_DIS_MODE SCLK12_13_POL SCLK12_13_HS
0x135 0 0 SCLK12_13_ADLY_EN SCLK12_13_ADLY
0x136 0 0 0 0 SCLK12_13_DDLY
0x137 CLKout13_FMT CLKout12_FMT
0x138 0 VCO_MUX OSCout_MUX OSCout_FMT
0x139 0 0 0 SYSREF_REQ_EN SYNC_BYPASS 0 SYSREF_MUX
0x13A 0 0 0 SYSREF_DIV[12:8]
0x13B SYSREF_DIV[7:0]
0x13C 0 0 0 SYSREF_DDLY[12:8]
0x13D SYSREF_DDLY[7:0]
0x13E 0 0 0 0 0 SYSREF_PULSE_CNT
0x13F PLL2_RCLK_
MUX		 0 PLL2_NCLK_
MUX		 PLL1_NCLK_MUX FB_MUX FB_MUX_EN
0x140 PLL1_PD VCO_LDO_PD VCO_PD OSCin_PD SYSREF_GBL_PD SYSREF_PD SYSREF_DDLY_PD SYSREF_PLSR_PD
0x141 DDLYd_
SYSREF_EN		 DDLYd12_EN DDLYd10_EN DDLYd8_EN DDLYd6_EN DDLYd4_EN DDLYd2_EN DDLYd0_EN
0x142 DDLYd_STEP_CNT
0x143 SYSREF_CLR SYNC_1SHOT_EN SYNC_POL SYNC_EN SYNC_PLL2_
DLD		 SYNC_PLL1_
DLD		 SYNC_MODE
0x144 SYNC_DISSYSREF SYNC_DIS12 SYNC_DIS10 SYNC_DIS8 SYNC_DIS6 SYNC_DIS4 SYNC_DIS2 SYNC_DIS0
0x145 0 PLL1R_SYNC_EN PLL1R_SYNC_SRC PLL2R_SYNC_EN 0 0 0
0x146 CLKin_SEL_PIN_EN CLKin_SEL_PIN_POL CLKin2_EN CLKin1_EN CLKin0_EN CLKin2_TYPE CLKin1_TYPE CLKin0_TYPE
0x147 CLKin_SEL_
AUTO_
REVERT_EN		 CLKin_SEL_
AUTO_EN		 CLKin_SEL_MANUAL CLKin1_DEMUX CLKin0_DEMUX
0x148 0 0 CLKin_SEL0_MUX CLKin_SEL0_TYPE
0x149 0 SDIO_RDBK_
TYPE		 CLKin_SEL1_MUX CLKin_SEL1_TYPE
0x14A 0 0 RESET_MUX RESET_TYPE
0x14B LOS_TIMEOUT LOS_EN TRACK_EN HOLDOVER_
FORCE		 MAN_DAC_EN MAN_DAC[9:8]
0x14C MAN_DAC[7:0]
0x14D 0 0 DAC_TRIP_LOW
0x14E DAC_CLK_MULT DAC_TRIP_HIGH
0x14F DAC_CLK_CNTR
0x150 0 CLKin_OVERRIDE HOLDOVER_
EXIT_MODE 		HOLDOVER_
PLL1_DET		 LOS_EXTERNAL_INPUT HOLDOVER_
VTUNE_DET		 CLKin_SWITCH
_CP_TRI		 HOLDOVER_
EN
0x151 0 0 HOLDOVER_DLD_CNT[13:8]
0x152 HOLDOVER_DLD_CNT[7:0]
0x153 0 0 CLKin0_R[13:8]
0x154 CLKin0_R[7:0]
0x155 0 0 CLKin1_R[13:8]
0x156 CLKin1_R[7:0]
0x157 0 0 CLKin2_R[13:8]
0x158 CLKin2_R[7:0]
0x159 0 0 PLL1_N[13:8]
0x15A PLL1_N[7:0]
0x15B PLL1_WND_SIZE PLL1_CP_TRI PLL1_CP_POL PLL1_CP_GAIN
0x15C 0 0 PLL1_DLD_CNT[13:8]
0x15D PLL1_DLD_CNT[7:0]
0x15E 0 0 0 HOLDOVER_EXIT_NADJ
0x15F PLL1_LD_MUX PLL1_LD_TYPE
0x160 0 0 0 0 PLL2_R
0x161 PLL2_R
0x162 PLL2_P 0 OSCin_FREQ PLL2_XTAL_EN PLL2_REF_2X_EN
0x163 0 0 0 0 0 0 PLL2_N_CAL[17:16]
0x164 PLL2_N_CAL[15:8]
0x165 PLL2_N_CAL[7:0]
0x166 0 0 0 0 0 0 PLL2_N[17:16]
0x167 PLL2_N[15:8]
0x168 PLL2_N[7:0]
0x169 0 PLL2_WND_SIZE PLL2_CP_GAIN PLL2_CP_POL PLL2_CP_TRI PLL2_DLD_EN
0x16A 0 0 PLL2_DLD_CNT[13:8]
0x16B PLL2_DLD_CNT[7:0]
0x16C 0 0 0 0 0 0 0 0
0x173 0 PLL2_PRE_PD PLL2_PD 0 0 0 0 0
0x177 PLL1R_RST
0x182 0 0 0 0 0 0 CLR_PLL1_LD_LOST CLR_PLL2_LD_LOST
0x183 0 0 0 0 RB_PLL1_DLD_LOST RB_PLL1_DLD RB_PLL2_DLD_LOST RB_PLL2_DLD
0x184 RB_DAC_VALUE[9:8] RB_CLKin2_
SEL		 RB_CLKin1_
SEL		 RB_CLKin0_
SEL		 RB_CLKin2_
LOS		 RB_CLKin1_
LOS		 RB_CLKin0_
LOS
0x185 RB_DAC_VALUE[7:0]
0x188 0 X RB_
HOLDOVER		 X RB_DAC_RAIL RB_DAC_HIGH RB_DAC_LOW RB_DAC_
LOCKED
0x555 SPI_LOCK