Ultra low-noise JESD204B compliant clock jitter cleaner with dual loop


Product details


Function Dual-loop PLL Number of outputs 15 RMS jitter (fs) 54 Output frequency (Min) (MHz) 0.305 Output frequency (Max) (MHz) 3250 Input type LVCMOS, LVDS, LVPECL Output type LVCMOS, LVDS, LVPECL Supply voltage (Min) (V) 3.15 Supply voltage (Max) (V) 3.45 Features JESD204B Operating temperature range (C) -40 to 85 open-in-new Find other Clock jitter cleaners & synchronizers

Package | Pins | Size

WQFN (NKD) 64 81 mm² 9 x 9 open-in-new Find other Clock jitter cleaners & synchronizers


  • Maximum Clock Output Frequency: 3255 MHz
  • Multi-Mode: Dual PLL, Single PLL, and Clock Distribution
  • Ultra-Low Noise, at 2500 MHz:
    • 54 fs RMS Jitter (12 kHz to 20 MHz)
    • 64 fs RMS Jitter (100 Hz to 20 MHz)
    • –157.6 dBc/Hz Noise Floor
  • Ultra-Low Noise, at 3200 MHz:
    • 61 fs RMS Jitter (12 kHz to 20 MHz)
    • 67 fs RMS Jitter (100 Hz to 100 MHz)
    • –156.5 dBc/Hz Noise Floor
  • PLL2
    • PLL FOM of –230 dBc/Hz
    • PLL 1/f of –128 dBc/Hz
    • Phase Detector Rate up to 320 MHz
    • Two Integrated VCOs: 2440 to 2580 MHz
      and 2945 to 3255 MHz
  • Up to 14 Differential Device Clocks
    • CML, LVPECL, LCPECL, HSDS, LVDS, and 2xLVCMOS Programmable Outputs
  • Up to 1 Buffered VCXO/XO Output
    • LVPECL, LVDS, 2xLVCMOS Programmable
  • 1-1023 CLKout Divider
  • 1-8191 SYSREF Divider
  • 25-ps Step Analog Delay for SYSREF Clocks
  • Digital Delay and Dynamic Digital Delay for Device Clock and SYSREF
  • Holdover Mode With PLL1
  • 0-Delay with PLL1 or PLL2
  • Supports 105°C PCB Temperature
    (Measured at Thermal Pad)
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The LMK04832 is an ultra-high performance clock conditioner with JEDEC JESD204B support and is also pin compatible with the LMK0482x family of devices.

The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high performance outputs for traditional clocking systems.

The LMK04832 can be configured for operation in dual PLL, single PLL, or clock distribution modes with or without SYSREF generation or reclocking. PLL2 may operate with either internal or external VCO.

The high performance combined with features like the ability to trade off between power and performance, dual VCOs, dynamic digital delay, and holdover make the LMK04832 ideal for providing flexible high performance clocking trees.

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Technical documentation

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Type Title Date
* Data sheet LMK04832 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs datasheet (Rev. C) May 25, 2018
Technical article Clock tree fundamentals: finding the right clocking devices for your design Mar. 24, 2021
Application note Clocking for Medical Ultrasound Systems (Rev. A) Sep. 30, 2020
Certificate LMK04832EVM-CVAL EU Declaration of Conformity (DoC) May 29, 2020
Application note Multi-Clock Synchronization Dec. 30, 2019
Technical article Step-by-step considerations for designing wide-bandwidth multichannel systems Jun. 04, 2019
User guide LMK04832EVM User’s Guide (Rev. A) Dec. 21, 2017
Application note Analog Applications Journal 2Q 2015 Apr. 28, 2015
Application note JESD204B multi-device synchronization: Breaking down the requirements Apr. 28, 2015
Application note When is the JESD204B interface the right choice? Jan. 22, 2014

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

document-generic User guide

The ADC12DJ3200EVMCVAL is an evaluation module (EVM) that evaluates the ADC12DJ3200QML-SP device. ADC12DJ3200QML-SP is a space-grade, low-power, 12-bit, dual 3.2-GSPS/single 6.4-GSPS, RF-sampling analog-to-digital converter (ADC) with a buffered analog input, integrated digital down converter (...)

  • Flexible transformer-coupled analog input to allow for a variety of sources and frequencies
  • Easy-to-use software GUI to configure ADC12DJ3200QML-SP, LMX2582, and LMK04832 devices for a variety of configurations through a USB interface
  • Quickly evaluate ADC performance through high-speed data converter (...)
document-generic User guide
The LMK04832EVM allows evaluation of the LMK04832 with test equipment or other evaluation boards to verify block or system requirements for use in a specific application.  The LMK04832 EVM is pre-populated with a 122.88 MHz VCXO for dual loop operation.  The VCXO can be substituted if a (...)
  • Up to three clocks inputs for PLL1 operation and up to four clock inputs for PLL2 operation
  • Buffered OSCin output on OSCout port.  If used, reduce one clock input
  • 14 clock outputs from internal VCO, external VCO, or clock input.  Plus one buffered OSCin output
  • SYNC input on CLKin0 or SYNC pin for (...)

Software development

Texas Instruments PLLatinum Simulator Tool
PLLATINUMSIM-SW The PLLATINUMSIM-SW simulator tool lets you create detailed designs and simulations of our PLLATINUM™ integrated circuits which include the LMX series of PLLs and synthesizers.
  • Part selection based on current, cost, phase noise and package
  • Filter design up for passive and active filters up to 4th-order
  • Simulation of phase noise including PLL, fractional engine, voltage-controlled oscillator (VCO), input, dividers, and loop filter
  • Simulation of spurs including phase detector (...)
Texas Instruments Clocks and Synthesizers (TICS) Pro Software
TICSPRO-SW The TICS Pro software is used to program the evaluation modules (EVMs) for device numbers with these prefixes: CDC, LMK and LMX. These devices include PLLs and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.
  • Program EVMs through the USB2ANY Interface Adaptor or onboard USB interface.
  • Export programming configurations for use in end application.

Design tools & simulation

SNAM221.ZIP (192 KB) - IBIS Model
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
Clock tree architect programming software
CLOCK-TREE-ARCHITECT Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
  • Accepts customer specific design requirements such as input frequencies, output frequencies, clock formats and clock counts
  • Generates clock trees by taking into account a variety of advanced specifications, such as noise floor and phase determinism requirements
  • Presents clear and intuitive block (...)

Reference designs

Multichannel RF transceiver reference design for radar and electronic warfare applications
TIDA-010132 — This reference design, an 8-channel analog front end (AFE), is demonstrated using two AFE7444 4-channel RF transceivers and a LMK04828-LMX2594 based clocking subsystem which can enable designs to scale to 16 or more channels. Each AFE channel consists of a 14-bit, 9-GSPS DAC and a 3-GSPS ADC that is (...)
document-generic Schematic document-generic User guide
Low noise power-supply reference design maximizing performance in 12.8 GSPS data acquisition systems
TIDA-01027 — This reference design demonstrates an efficient, low noise 5-rail power-supply design for very high-speed DAQ systems capable of > 12.8 GSPS. The power supply DC/DC converters are frequency synchronized and phase-shifted in order to minimize input current ripple and control frequency content (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

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WQFN (NKD) 64 View options

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