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LMK04832

ACTIVE

Ultra-low-noise, 3.2-GHz, 15-output, JESD204B clock jitter cleaner with dual loop

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Data sheet

LMK04832

ACTIVE
Data sheet Order now

Product details

Number of input channels 3 Number of outputs 15 RMS jitter (fs) 54 Features JESD204B Output frequency (min) (MHz) 0.305 Output frequency (max) (MHz) 3250 Output type LVCMOS, LVDS, LVPECL Input type LVCMOS, LVDS, LVPECL Operating temperature range (°C) -40 to 85
Number of input channels 3 Number of outputs 15 RMS jitter (fs) 54 Features JESD204B Output frequency (min) (MHz) 0.305 Output frequency (max) (MHz) 3250 Output type LVCMOS, LVDS, LVPECL Input type LVCMOS, LVDS, LVPECL Operating temperature range (°C) -40 to 85
WQFN (NKD) 64 81 mm² (9 mm × 9 mm)
  • Maximum Clock Output Frequency: 3255 MHz
  • Multi-Mode: Dual PLL, Single PLL, and Clock Distribution
  • Ultra-Low Noise, at 2500 MHz:
    • 54 fs RMS Jitter (12 kHz to 20 MHz)
    • 64 fs RMS Jitter (100 Hz to 20 MHz)
    • –157.6 dBc/Hz Noise Floor
  • Ultra-Low Noise, at 3200 MHz:
    • 61 fs RMS Jitter (12 kHz to 20 MHz)
    • 67 fs RMS Jitter (100 Hz to 100 MHz)
    • –156.5 dBc/Hz Noise Floor
  • PLL2
    • PLL FOM of –230 dBc/Hz
    • PLL 1/f of –128 dBc/Hz
    • Phase Detector Rate up to 320 MHz
    • Two Integrated VCOs: 2440 to 2580 MHz
      and 2945 to 3255 MHz
  • Up to 14 Differential Device Clocks
    • CML, LVPECL, LCPECL, HSDS, LVDS, and 2xLVCMOS Programmable Outputs
  • Up to 1 Buffered VCXO/XO Output
    • LVPECL, LVDS, 2xLVCMOS Programmable
  • 1-1023 CLKout Divider
  • 1-8191 SYSREF Divider
  • 25-ps Step Analog Delay for SYSREF Clocks
  • Digital Delay and Dynamic Digital Delay for Device Clock and SYSREF
  • Holdover Mode With PLL1
  • 0-Delay with PLL1 or PLL2
  • Supports 105°C PCB Temperature
    (Measured at Thermal Pad)
  • Maximum Clock Output Frequency: 3255 MHz
  • Multi-Mode: Dual PLL, Single PLL, and Clock Distribution
  • Ultra-Low Noise, at 2500 MHz:
    • 54 fs RMS Jitter (12 kHz to 20 MHz)
    • 64 fs RMS Jitter (100 Hz to 20 MHz)
    • –157.6 dBc/Hz Noise Floor
  • Ultra-Low Noise, at 3200 MHz:
    • 61 fs RMS Jitter (12 kHz to 20 MHz)
    • 67 fs RMS Jitter (100 Hz to 100 MHz)
    • –156.5 dBc/Hz Noise Floor
  • PLL2
    • PLL FOM of –230 dBc/Hz
    • PLL 1/f of –128 dBc/Hz
    • Phase Detector Rate up to 320 MHz
    • Two Integrated VCOs: 2440 to 2580 MHz
      and 2945 to 3255 MHz
  • Up to 14 Differential Device Clocks
    • CML, LVPECL, LCPECL, HSDS, LVDS, and 2xLVCMOS Programmable Outputs
  • Up to 1 Buffered VCXO/XO Output
    • LVPECL, LVDS, 2xLVCMOS Programmable
  • 1-1023 CLKout Divider
  • 1-8191 SYSREF Divider
  • 25-ps Step Analog Delay for SYSREF Clocks
  • Digital Delay and Dynamic Digital Delay for Device Clock and SYSREF
  • Holdover Mode With PLL1
  • 0-Delay with PLL1 or PLL2
  • Supports 105°C PCB Temperature
    (Measured at Thermal Pad)

The LMK04832 is an ultra-high performance clock conditioner with JEDEC JESD204B support and is also pin compatible with the LMK0482x family of devices.

The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high performance outputs for traditional clocking systems.

The LMK04832 can be configured for operation in dual PLL, single PLL, or clock distribution modes with or without SYSREF generation or reclocking. PLL2 may operate with either internal or external VCO.

The high performance combined with features like the ability to trade off between power and performance, dual VCOs, dynamic digital delay, and holdover make the LMK04832 ideal for providing flexible high performance clocking trees.

The LMK04832 is an ultra-high performance clock conditioner with JEDEC JESD204B support and is also pin compatible with the LMK0482x family of devices.

The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high performance outputs for traditional clocking systems.

The LMK04832 can be configured for operation in dual PLL, single PLL, or clock distribution modes with or without SYSREF generation or reclocking. PLL2 may operate with either internal or external VCO.

The high performance combined with features like the ability to trade off between power and performance, dual VCOs, dynamic digital delay, and holdover make the LMK04832 ideal for providing flexible high performance clocking trees.
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Technical documentation

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* Data sheet LMK04832 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs datasheet (Rev. C) PDF | HTML May 25, 2018
Application note Practical Clocking Considerations That Give Your Next High-Speed Converter Design an Edge (Rev. A) PDF | HTML Apr 11, 2025
Application note Sine to Square Wave Conversion Using Clock Buffers PDF | HTML Sep 3, 2024
Technical article Clock tree fundamentals: finding the right clocking devices for your design PDF | HTML Mar 24, 2021
Application note Clocking for Medical Ultrasound Systems (Rev. A) PDF | HTML Sep 30, 2020
Certificate LMK04832EVM-CVAL EU Declaration of Conformity (DoC) May 29, 2020
Application note Multi-Clock Synchronization Dec 30, 2019
Technical article Step-by-step considerations for designing wide-bandwidth multichannel systems PDF | HTML Jun 4, 2019
Analog design Journal Analog Applications Journal 2Q 2015 Apr 28, 2015
Analog design Journal JESD204B multi-device synchronization: Breaking down the requirements Apr 28, 2015
Analog design Journal When is the JESD204B interface the right choice? Jan 22, 2014

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

ADC12DJ3200EVMCVAL — ADC12DJ3200QML-SP evaluation module

The ADC12DJ3200 evaluation module (EVM) is designed to evaluate the ADC12DJ3200QML-SP high-speed analog-to-digital converters (ADCs). The EVM is populated with the ADC12DJ3200QML-SP, a space-grade 12-bit, dual-channel 4GSPS or single-channel 8GSPS ADC with JESD204B interface.
User guide: PDF
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Evaluation board

LMK04832EVM — LMK04832 JESD204B Clock Jitter Cleaner/Clock Generator/Distribution Evaluation Module

The LMK04832 evaluation module (EVM) allows evaluation of the LMK04832 with test equipment or other evaluation boards to verify block or system requirements for use in a specific application.

LMK04832EVM is prepopulated with a 122.88-MHz VCXO for dual-loop operation. The VCXO can be (...)

User guide: PDF
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Support software

TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices

Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.

Supported products & hardware
Simulation model

LMK04832 IBIS Model

SNAM221.ZIP (192 KB) - IBIS model
Supported products & hardware
Design tool

CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.

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Design tool

PLLATINUMSIM-SW — PLL loop filter, phase noise, lock time, and spur simulation tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

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Reference design

TIDA-010132 — Multichannel RF transceiver reference design for radar applications

This reference design, an 8-channel analog front end (AFE), uses two AFE7444 4-channel RF transceivers and LMK04828-LMX2594-based clocking subsystem which can enable designs to scale to 16 channels or more. Each AFE channel consists of a 14-bit, 9GSPS DAC and a 3GSPS ADC that is synchronized to (...)

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Reference design

TIDA-010230 — Multi-channel RF transceiver, low-noise clocking reference design for radar and EW applications

In modern radar and electronic warfare (EW) systems, active electronically-scanned array (AESA) antenna systems are often used with high speed multi-channel RF transceivers. These systems require very low noise clocking capable of precise channel-to-channel skew adjustment to achieve the optimal (...)
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Reference design

TIDA-01027 — Low-noise power supply reference design maximizing performance in 12.8-GSPS data acquisition systems

This reference design demonstrates an efficient, low-noise five-rail power supply design for very high-speed Data Acquisition (DAQ) systems capable of > 12.8 GSPS. The power supply DC/DC converters are frequency-synchronized and phase-shifted in order to minimize input current ripple and (...)
Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
WQFN (NKD) 64 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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