SNAS859 March 2024 LMK05318B-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
Hitless switching between 1-PPS inputs is supported, but the switchover event must only occur after the DPLL has acquired lock. If a switchover occurs before the DPLL has locked initially, the switchover is not hitless and the DPLL takes an indeterminate amount of time to lock. In this case, issue a soft-reset for the DPLL to lock to the selected input. In an application, the system host can monitor the DPLL lock status through a STATUS pin or bit to determine when the DPLL has locked before allowing a switchover between 1-PPS inputs. The DPLL lock time is governed by the DPLL bandwidth (typically 10mHz for a 1-PPS input).