SNAS859 March 2024 LMK05318B-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
After device POR configuration and initialization, APLL1 automatically locks to the XO clock when the clock is detected by the APLL1 input monitor. Then, APLL2 acquires a lock to either VCO1 or XO frequency as selected. The output clock frequency accuracy and stability in free-run mode are equal to that of the XO input. The reference inputs remain invalid (unqualified) during free-run mode.