Unless otherwise noted: VDD = 3.3V, VDDO = 1.8V, TA = 25°C, AC-LVPECL output measured. DPLL: fREF = 25MHz, fTDC = 25MHz, BWDPLL = 10Hz, DPLL locked to reference. APLL1: fXO = 48MHz, fPD1 = 24MHz (fXO÷2), fVCO1 = 2500MHz, BWAPLL1 = 2.5kHz, DPLL mode. APLL2: fPD2 = 138.8MHz (fVCO1÷18), BWAPLL2 = 500kHz, Cascaded APLL2 mode for Figure 5-10 and Figure 5-11.The PLL output clock phase noise at different frequency offsets are determined by different noise contributors, such as external clock input sources (REF IN, OCXO, XO) and internal noise sources (PLL, VCO), as well as the configured PLL loop bandwidths (BWREF-DPLL, BWTCXO-DPLL, BWAPLL). The phase noise profile shown for each external clock source (fSOURCE) was normalized to the PLL output frequency (fOUT) by adding 20×LOG10(fOUT / fSOURCE) to the measured phase noise of the source.
![LMK05318B-Q1 625MHz Output Phase Noise
(APLL1) GUID-6272A198-5D39-45F8-B844-3279FC239C55-low.png](/ods/images/SNAS859/GUID-6272A198-5D39-45F8-B844-3279FC239C55-low.png)
Jitter = 40fs RMS
(12kHz to 20MHz) |
DPLL Mode (APLL2
Disabled) |
Figure 5-5 625MHz Output Phase Noise
(APLL1)![LMK05318B-Q1 156.25MHz Output Phase Noise (APLL1) GUID-B50AE0FA-F19F-4552-BE9B-A3B128E9E3E5-low.png](/ods/images/SNAS859/GUID-B50AE0FA-F19F-4552-BE9B-A3B128E9E3E5-low.png)
Jitter = 56fs RMS
(12kHz to 20MHz) |
DPLL Mode (APLL2
Disabled) |
Figure 5-7 156.25MHz Output Phase Noise (APLL1)![LMK05318B-Q1 100MHz Output Phase Noise
(APLL1) GUID-5B93D8CE-2A4B-4E37-AFFB-FE030270C0AE-low.png](/ods/images/SNAS859/GUID-5B93D8CE-2A4B-4E37-AFFB-FE030270C0AE-low.png)
Jitter = 74fs RMS
(12kHz to 20MHz) |
DPLL Mode (APLL2
Disabled) |
|
Figure 5-9 100MHz Output Phase Noise
(APLL1)![LMK05318B-Q1 212.5MHz Output Phase
Noise (APLL2) GUID-9041FCDA-BDB6-4699-9AF3-1DC455EBD558-low.png](/ods/images/SNAS859/GUID-9041FCDA-BDB6-4699-9AF3-1DC455EBD558-low.png)
Jitter = 120fs
RMS (12kHz to 20MHz) |
DPLL Mode With
Cascaded APLL2 |
fVCO2
= 5737.5MHz |
Figure 5-11 212.5MHz Output Phase
Noise (APLL2)![LMK05318B-Q1 PSNR vs Noise Frequency
(25mVpp) For 156.25MHz Output GUID-B997B0C7-7693-486B-A257-612C2DF85746-low.gif](/ods/images/SNAS859/GUID-B997B0C7-7693-486B-A257-612C2DF85746-low.gif)
25mVpp
noise injected onto supplies (VDD = 3.3V, VDDO =
1.8V) |
DJSPUR (ps pk-pk) = 2 ×
10(dBc/20) / (π × fOUT) × 1E6,
where dBc is the PSNR spur level (in dBc) and
fOUT is the output frequency (in
MHz) |
Figure 5-13 PSNR vs Noise Frequency
(25mVpp) For 156.25MHz Output ![LMK05318B-Q1 312.5MHz Output Phase Noise (APLL1) GUID-1876ADE7-1713-4E65-95B7-14ED532B3594-low.png](/ods/images/SNAS859/GUID-1876ADE7-1713-4E65-95B7-14ED532B3594-low.png)
Jitter = 47fs RMS
(12kHz to 20MHz) |
DPLL Mode (APLL2
Disabled) |
Figure 5-6 312.5MHz Output Phase Noise (APLL1)![LMK05318B-Q1 125MHz Output Phase Noise (APLL1) GUID-0147AF57-5C05-4BA2-99C8-C8564CF31E7F-low.png](/ods/images/SNAS859/GUID-0147AF57-5C05-4BA2-99C8-C8564CF31E7F-low.png)
Jitter = 63fs RMS
(12kHz to 20MHz) |
DPLL Mode (APLL2
Disabled) |
Figure 5-8 125MHz Output Phase Noise (APLL1)![LMK05318B-Q1 155.52MHz Output Phase
Noise (APLL2) GUID-67D20B2B-5C16-4E1B-A908-F3A5E586B76F-low.png](/ods/images/SNAS859/GUID-67D20B2B-5C16-4E1B-A908-F3A5E586B76F-low.png)
Jitter = 117fs
RMS (12kHz to 20MHz) |
DPLL Mode With
Cascaded APLL2 |
fVCO2
= 5598.72MHz |
Figure 5-10 155.52MHz Output Phase
Noise (APLL2)![LMK05318B-Q1 PSNR vs Noise Frequency
(50mVpp) For 156.25MHz Output GUID-D2BBAD74-5728-4DB6-90A0-C3B91C951978-low.gif](/ods/images/SNAS859/GUID-D2BBAD74-5728-4DB6-90A0-C3B91C951978-low.gif)
50mVpp
noise injected onto supplies (VDD = 3.3V, VDDO =
3.3V) |
|
Figure 5-12 PSNR vs Noise Frequency
(50mVpp) For 156.25MHz Output
Figure 5-14 Output Swing vs
Frequency