SNAS947 May   2025 LMK1C1102A , LMK1C1103A , LMK1C1104A , LMK1C1106A , LMK1C1108A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Fail-Safe Inputs
      2. 8.3.2 Asynchronous Output Enable
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.1 Design Requirements

The LMK1C110xA shown in Figure 9-1 is configured to fan out a 100-MHz signal from a local LVCMOS oscillator. The CPU is configured to control the output state through 1G.

The configuration example is driving three LVCMOS receivers in a backplane application with the following properties:

  • The CPU clock can accept a full swing DC-coupled LVCMOS signal. A series resistor RS is placed near the LMK1C110xA to closely match the characteristic impedance of the trace to minimize reflections.
  • The FPGA clock is similarly DC-coupled with an appropriate series resistor placed near the LMK1C110xA.
  • The PLL in this example can accept a lower amplitude signal, so a Thevenin's equivalent termination (pull up to VDD and pull down to GND) is used. The PLL receiver features internal biasing, so AC coupling can be used when common-mode voltage is mismatched.