SNAS947 May 2025 LMK1C1102A , LMK1C1103A , LMK1C1104A , LMK1C1106A , LMK1C1108A
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
Figure 5-7 LMK1C1108A, 16-Pin PW TSSOP Package (Top
View)
Figure 5-6 LMK1C1106A, 14-Pin PW TSSOP Package (Top
View)| PIN | TYPE | DESCRIPTION | |||||
|---|---|---|---|---|---|---|---|
| NAME | LMK1C 1102A |
LMK1C 1103A |
LMK1C 1104A |
LMK1C 1106A |
LMK1C 1108A |
||
| LVCMOS CLOCK INPUT | |||||||
| CLKIN | 1 | 1 | 1 | 1 | 1 | Input | Single-ended clock input with internal 300-kΩ (typical) pulldown resistor to GND. Typically connected to a single-ended clock input. |
| CLOCK OUTPUT ENABLE | |||||||
| 1G | 2 | 2 | 2 | 2 | 2 | Input | Global Output Enable with internal 300-kΩ
(typical) pulldown resistor to GND. Typically connected to VDD
with external pullup resistor. HIGH: outputs enabled LOW: outputs disabled |
| LVCMOS CLOCK OUTPUT | |||||||
| Y0 | 3 | 3 | 3 | 3 | 3 | Output | LVCMOS output. Typically connected to a receiver. Unused outputs can be left floating. |
| Y1 | 8 | 8 | 8 | 14 | 16 | ||
| Y2 | — | 5 | 5 | 11 | 13 | ||
| Y3 | — | — | 7 | 13 | 15 | ||
| Y4 | — | — | — | 6 | 6 | ||
| Y5 | — | — | — | 9 | 11 | ||
| Y6 | — | — | — | — | 8 | ||
| Y7 | — | — | — | — | 9 | ||
| SUPPLY VOLTAGE | |||||||
| VDD | 6 | 6 | 6 | 5 | 5 | Power | Power supply terminal. Typically connected to a 3.3-V, 2.5-V, or 1.8-V supply. The VDD pin is typically connected to an external 0.1-μF capacitor near the pin. |
| 8 | 10 | ||||||
| 12 | 14 | ||||||
| GROUND | |||||||
| GND | 4 | 4 | 4 | 4 | 4 | GND | Power supply ground. |
| 7 | 7 | ||||||
| 10 | 12 | ||||||