Product details

Number of outputs 2 Additive RMS jitter (typ) (fs) 19.2 Core supply voltage (V) 1.8, 2.5, 3.3 Output supply voltage (V) 1.8, 2.5, 3.3 Output skew (ps) 25 Operating temperature range (°C) -40 to 125 Rating Catalog Output type LVCMOS Input type LVCMOS
Number of outputs 2 Additive RMS jitter (typ) (fs) 19.2 Core supply voltage (V) 1.8, 2.5, 3.3 Output supply voltage (V) 1.8, 2.5, 3.3 Output skew (ps) 25 Operating temperature range (°C) -40 to 125 Rating Catalog Output type LVCMOS Input type LVCMOS
TSSOP (PW) 8 19.2 mm² 3 x 6.4 WSON (DQF) 8 4 mm² 2 x 2
  • High-performance 1:2, 1:3, 1:4, 1:6 and 1:8 LVCMOS clock buffer
  • Very low output skew:
    • LMK1C1102A, LMK1C1103A and LMK1C1104A < 50ps
    • LMK1C1106 and LMK1C1108 < 55ps
  • Extremely low additive jitter:
    • LMK1C1102A, LMK1C1103A and LMK1C1104A
      • 7.5fs typical at VDD = 3.3V
      • 10fs typical at VDD = 2.5V
      • 19.2fs typical at VDD = 1.8V
    • LMK1C1106A and LMK1C1108A
      • 12fs typical at VDD = 3.3V
      • 15fs typical at VDD = 2.5V
      • 28fs typical at VDD = 1.8V
  • Very low propagation delay < 3ns
  • Asynchronous output enable
  • Supply voltage: 3.3V, 2.5V, or 1.8V
    • Fail-safe inputs: 3.3V tolerant input at all supply voltages
  • fmax = 250MHz for 3.3V fmax = 200MHz for 2.5V or 1.8V
  • Operating temperature range: –40°C to 125°C
  • High-performance 1:2, 1:3, 1:4, 1:6 and 1:8 LVCMOS clock buffer
  • Very low output skew:
    • LMK1C1102A, LMK1C1103A and LMK1C1104A < 50ps
    • LMK1C1106 and LMK1C1108 < 55ps
  • Extremely low additive jitter:
    • LMK1C1102A, LMK1C1103A and LMK1C1104A
      • 7.5fs typical at VDD = 3.3V
      • 10fs typical at VDD = 2.5V
      • 19.2fs typical at VDD = 1.8V
    • LMK1C1106A and LMK1C1108A
      • 12fs typical at VDD = 3.3V
      • 15fs typical at VDD = 2.5V
      • 28fs typical at VDD = 1.8V
  • Very low propagation delay < 3ns
  • Asynchronous output enable
  • Supply voltage: 3.3V, 2.5V, or 1.8V
    • Fail-safe inputs: 3.3V tolerant input at all supply voltages
  • fmax = 250MHz for 3.3V fmax = 200MHz for 2.5V or 1.8V
  • Operating temperature range: –40°C to 125°C

The LMK1C110xA is a modular, high-performance, low-skew, general-purpose clock buffer family from Texas Instruments. The entire family is designed with a modular approach in mind. Five different fan-out variations, 1:2, 1:3, 1:4, 1:6 and 1:8 are available.

All of the devices within this family are pin-compatible to each other and backwards compatible to the CDCLVC110x family for easy handling.

The LMK1C110xA supports a asynchronous output enable control (1G) which switches the outputs into a low state when 1G is low. Asynchronous enable and disable is helpful for 1PPS applications and DC inputs operations. These devices have a fail-safe input that prevents oscillation at the outputs in the absence of an input signal and allows for input signals before VDD is supplied.

The LMK1C110xA is a modular, high-performance, low-skew, general-purpose clock buffer family from Texas Instruments. The entire family is designed with a modular approach in mind. Five different fan-out variations, 1:2, 1:3, 1:4, 1:6 and 1:8 are available.

All of the devices within this family are pin-compatible to each other and backwards compatible to the CDCLVC110x family for easy handling.

The LMK1C110xA supports a asynchronous output enable control (1G) which switches the outputs into a low state when 1G is low. Asynchronous enable and disable is helpful for 1PPS applications and DC inputs operations. These devices have a fail-safe input that prevents oscillation at the outputs in the absence of an input signal and allows for input signals before VDD is supplied.

Download View video with transcript Video

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 1
Top documentation Type Title Format options Date
* Data sheet LMK1C110xA 1.8V, 2.5V, and 3.3V Low Noise Asynchronous LVCMOS Clock Buffer Family datasheet PDF | HTML 27 May 2025

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Design tool

PLLATINUMSIM-SW PLL loop filter, phase noise, lock time, and spur simulation tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

Supported products & hardware

Supported products & hardware

Download options
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Package Pins CAD symbols, footprints & 3D models
TSSOP (PW) 8 Ultra Librarian
WSON (DQF) 8 Ultra Librarian

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos