COMMON MODE REJECTION RATIO is a measure of how well in-phase signals common to both input pins are rejected. To calculate CMRR, the change in output offset is measured while the common mode input voltage is changed.
CMRR = 20 LOG(ΔCommon Input / ΔOutput Offset)
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) – says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. LMP90080’s ENOB is a DC ENOB spec, not the dynamic ENOB that is measured using FFT and SINAD. Its equation is as follows:
GAIN ERROR is the deviation from the ideal slope of the transfer function.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a straight line through the input to output transfer function. The deviation of any given code from this straight line is measured from the center of that code value. The end point fit method is used. INL for this product is specified over a limited range, per the Electrical Tables.
NEGATIVE FULL-SCALE ERROR is the difference between the differential input voltage at which the output code transitions to negative full scale and (-VREF + 1LSB).
NEGATIVE GAIN ERROR is the difference between the negative full-scale error and the offset error divided by (VREF / Gain).
NOISE FREE RESOLUTION is a method of specifying the number of bits for a converter with noise.
ODR Output Data Rate.
OFFSET ERROR is the difference between the differential input voltage at which the output code transitions from code 0000h to 0001h and 1 LSB.
POSITIVE FULL-SCALE ERROR is the difference between the differential input voltage at which the output code transitions to positive full scale and (VREF – 1LSB).
POSITIVE GAIN ERROR is the difference between the positive full-scale error and the offset error divided by (VREF / Gain).
POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well a change in the analog supply voltage is rejected. PSRR is calculated from the ratio of the change in offset error for a given change in supply voltage, expressed in dB.
PSRR = 20 LOG (ΔVA / ΔOutput Offset)
The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy.
|PARTS||PRODUCT FOLDER||SAMPLE & BUY||TECHNICAL DOCUMENTS||TOOLS & SOFTWARE||SUPPORT & COMMUNITY|
|LMP90077||Click here||Click here||Click here||Click here||Click here|
|LMP90078||Click here||Click here||Click here||Click here||Click here|
|LMP90079||Click here||Click here||Click here||Click here||Click here|
|LMP90080||Click here||Click here||Click here||Click here||Click here|
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.