SLUSF64B August   2024  – January 2025 LMR51625 , LMR51635

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fixed Frequency Peak Current Mode Control
      2. 7.3.2 Adjustable Output Voltage
      3. 7.3.3 Enable
      4. 7.3.4 Minimum ON Time, Minimum OFF Time, and Frequency Foldback
      5. 7.3.5 Bootstrap Voltage
      6. 7.3.6 Overcurrent and Short-Circuit Protection
      7. 7.3.7 Soft Start
      8. 7.3.8 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Active Mode
      3. 7.4.3 CCM Mode
      4. 7.4.4 Light Load Operation (PFM Version)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Output Voltage Set-Point
        3. 8.2.2.3 Switching Frequency
        4. 8.2.2.4 Inductor Selection
        5. 8.2.2.5 Output Capacitor Selection
        6. 8.2.2.6 Input Capacitor Selection
        7. 8.2.2.7 Bootstrap Capacitor
        8. 8.2.2.8 Undervoltage Lockout Set-Point
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Compact Layout for EMI Reduction
        2. 8.4.1.2 Feedback Resistors
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Limits apply over operating junction temperature (TJ) range of –40°C to +150°C, unless otherwise stated. Minimum and Maximum limits(1) are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 4.3V to 60V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ(VIN) VIN quiescent current (non-switching)(2) VEN = 3V, PFM variant only 26 46 µA
ISUPPLY Input supply current when in
regulation(3)		 VIN = 24V, VOUT = 3.3V, IOUT = 0A,
RFBT = 1MΩ, PFM variant		 29 µA
ISD(VIN) VIN shutdown supply current VEN = 0V 2.0   µA
UVLO
VIN_UVLO(R) VIN UVLO rising threshold  VIN rising 4.0 4.25 V
VIN_UVLO(F) VIN UVLO falling threshold VIN falling 3.8 V
VIN_UVLO(H) VIN UVLO hysteresis 0.2 V
ENABLE
VEN(R) EN voltage rising threshold EN rising, enable switching 1.103 1.226 1.349 V
VEN(F) EN voltage falling threshold EN falling, disable switching 0.887 0.985 1.084 V
IEN(P2) EN pin sourcing current post EN rising threshold VEN = 3V 10 50 nA
REFERENCE VOLTAGE
VFB Reference voltage 0.792 0.8 0.808 V
IFB(LKG) FB input leakage current VFB = 0.8V 0.2 nA
SWITCHING FREQUENCY
fSW1(CCM) Switching frequency, CCM operation "Y" version, VIN = 24V 0.99 1.1 1.21 MHz
fSW1(CCM) Switching frequency, CCM operation "X" version, VIN = 24V 360 400 440 kHz
FDither Switching frequency dithering(3) PFM option, requency
dithering over center frequency		   ±8.5%    
START-UP
tSS Internal fixed soft-start time The time of internal reference to increase from 0.08V to 0.72V 4.0 ms
POWER STAGE
RDSON(HS) High-side MOSFET on-resistance ISW = –100mA 85 mΩ
RDSON(LS) Low-side MOSFET on-resistance ISW = 100mA 45 mΩ
tON-MIN Minimum ON pulse width VIN = 24V, IOUT = 1A 70 ns
tON-MAX Maximum ON pulse width VIN = 24V, IOUT = 1A 5 µs
tOFF-MIN Minimum OFF pulse width VIN = 24V 200 ns
CURRENT LIMITS AND HICCUP
IHS_PK(OC) High-side peak current limit (4) 3.5A version  4.2 5.1 6.0 A
High-side peak current limit (4) 2.5A version 2.9 3.7 4.5 A
ILS_V(OC) Low-side valley current limit (4) 3.5A version  3.2 4.0 4.8 A
Low-side valley current limit (4) 2.5A version 2.3 2.8 3.3 A
ILS(NOC) Low-side negative current limit(4)  FPWM option, 3.5A version –3.0 A
Low-side negative current limit(4)  FPWM option, 2.5A version –2.0 A
IZC Zero-cross detection current threshold 0 A
VHICCUP FB pin voltage required to trip short circuit hiccup mode (3) 0.32 V
tHICCUP Time between current-limit hiccup
burst (3)		 85 ms
THERMAL SHUTDOWN
TJ(SD) Thermal shutdown threshold (3) Temperature rising 165 °C
TJ(HYS) Thermal shutdown hysteresis (3) 20 °C
(1) MIN and MAX limits are 100% production tested at 25℃. Limits over the operating temperature range verified through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) This is the current used by the device open loop. The value does not represent the total input current of the system when in regulation.
(3) Not production tested. Specified by correlation by design.
(4) The current limit values in this table are tested, open loop, in production. These values can differ from those found in a closed loop application.