SLUSEG8B October 2021 – February 2022 LMR54406 , LMR54410

PRODUCTION DATA

- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information

- DBV|6

The device is designed to be used with
a wide variety of LC filters. It is generally desired to minimize the output
capacitance to keep cost and size down. The output capacitor or capacitors,
C_{OUT}, must be chosen with care since it directly affects the steady
state output voltage ripple, loop stability, and output voltage overshoot and
undershoot during load current transient. The output voltage ripple is essentially
composed of two parts. One part is caused by the inductor ripple current flowing
through the Equivalent Series Resistance (ESR) of the output capacitors:

Equation 10.

The other part is caused by the inductor current ripple charging and discharging the output capacitors:

Equation 11.

The two components of the voltage ripple are not in-phase, therefore, the actual peak-to-peak ripple is less than the sum of the two peaks.

Output capacitance is usually limited
by transient performance specifications if the system requires tight voltage
regulation with presence of large current steps and fast slew rates. When a large
load step occurs, output capacitors provide the required charge before the inductor
current can slew to an appropriate level. The control loop of the converter usually
requires eight or more clock cycles to regulate the inductor current equal to the
new load level during this time. The output capacitance must be large enough to
supply the current difference for eight clock cycles to maintain the output voltage
within the specified range. Equation 12 shows the minimum output capacitance needed for a specified
V_{OUT} overshoot and undershoot.

Equation 12.

where

- K
_{IND}= Ripple ratio of the inductor current (Δi_{L}/ I_{OUT}) - I
_{OL}= Low level output current during load transient - I
_{OH}= High level output current during load transient - V
_{OUT_SHOOT}= Target output voltage overshoot or undershoot

For this design example, the target
output ripple is 30 mV. Assuming ΔV_{OUT_ESR} = ΔV_{OUT_C} = 30 mV,
choose K_{IND} = 0.4. Equation 10 yields ESR no larger than 75 mΩ and Equation 11 yields C_{OUT} no smaller than 2.38 µF. For the target overshoot and undershoot limitation of this
design, ΔV_{OUT_SHOOT} = 8% × V_{OUT} = 400 mV. The C_{OUT}
can be calculated to be no less than 14.3 µF by Equation 12. In summary, the most stringent criteria for the output
capacitor is 14.3 µF. Considering derating, one 22-µF, 10-V, X7R ceramic capacitor with 10-mΩ ESR is used.