SNVS311D May   2005  – February 2015 LP3878-ADJ

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Shutdown Input Operation
      2. 7.3.2 Reverse Input-Output Voltage
      3. 7.3.3 Low Output Noise
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With VOUT(TARGET) + 2 V ≤ VIN ≤ 16 V
      2. 7.4.2 Operation With SHUTDOWN Pin Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External Capacitors
          1. 8.2.2.1.1 Input Capacitor
          2. 8.2.2.1.2 Output Capacitor
          3. 8.2.2.1.3 Noise Bypass Capacitor
        2. 8.2.2.2 Feedforward Capacitor
        3. 8.2.2.3 Capacitor Characteristics
          1. 8.2.2.3.1 Ceramic
        4. 8.2.2.4 Setting the Output Voltage
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

SO PowerPAD (DDA) Package
8-Pin
Top View
LP3878-ADJ powerpad_snvs311.gif
WSON (NGT) Package
8-Pin
Top View
LP3878-ADJ WSON_snvs311.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NUMBER
ADJ 6 I Provides feedback to error amplifier from the resistive divider that sets the output voltage.
BYPASS 1 — The capacitor connected between BYPASS and GROUND lowers output noise voltage level and is required for loop stability.
GROUND 3 — Device ground.
IN 4 I Input source voltage.
N/C 2 DO NOT CONNECT. Device pin 2 is reserved for post packaging test and calibration of the LP3878-ADJ VADJ accuracy. This pin must be left floating. Do not connect to any potential. Do not connect to ground. Any attempt to do pin continuity testing on device pin 2 is discouraged. Continuity test results will be variable depending on the actions of the factory calibration. Aggressive pin continuity testing (high voltage, or high current) on device pin 2 may activate the trim circuitry forcing VADJ to move out of tolerance.
N/C 7 No internal connection.
OUT 5 O Regulated output voltage.
SHUTDOWN 8 I Output is enabled above turnon threshold voltage. Pull down to turn off regulator output.
Thermal Pad — — The exposed thermal pad on the bottom of the package should be connected to a copper thermal pad on the PCB under the package. The use of thermal vias to remove heat from the package into the PCB is recommended. Connect the thermal pad to ground potential or leave floating. Do not connect the thermal pad to any potential other than the same ground potential seen at device pin 3. For additional information on using TI's Non Pull Back WSON package, see Application Note AN-1187, SNOA401.