Product details


Output options Adjustable Output Iout (Max) (A) 0.8 Vin (Max) (V) 16 Vin (Min) (V) 2.5 Vout (Max) (V) 5.5 Vout (Min) (V) 1 Noise (uVrms) 18 Iq (Typ) (mA) 5.5 Thermal resistance θJA (°C/W) 43 Load capacitance (Min) (µF) 10 Rating Catalog Regulated outputs (#) 1 Features Enable Accuracy (%) 3 PSRR @ 100 KHz (dB) 35 Dropout voltage (Vdo) (Typ) (mV) 475 Operating temperature range (C) -40 to 125 open-in-new Find other Linear regulators (LDO)

Package | Pins | Size

HSOIC (DDA) 8 19 mm² 4.9 x 3.9 WSON (NGT) 8 16 mm² 4 x 4 open-in-new Find other Linear regulators (LDO)


  • Input Supply Voltage: 2.5 V to 16V
  • Output Voltage Range: 1 V to 5.5 V
  • Designed for Use With Low-ESR Ceramic
  • Very Low Output Noise
  • 8-Lead SO PowerPAD and WSON Surface-
    Mount Packages
  • < 10-µA Quiescent Current in Shutdown
  • Low Ground Pin Current at all Loads
  • Overtemperature and Overcurrent Protection
  • –40°C to 125°C Operating Junction Temperature
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The LP3878-ADJ is an 800-mA, adjustable output, voltage regulator designed to provide high performance and low noise in applications requiring output voltages as low as 1 V.

Using an optimized VIP (Vertically Integrated PNP) process, the LP3878-ADJ delivers superior performance:

  • Ground Pin Current: Typically 5.5 mA at 800-mA load, and 180 µA at 100-µA load.
  • Low Power Shutdown: The LP3878-ADJ draws less than 10-µA quiescent current when the SHUTDOWN pin is pulled low.
  • Precision Output: Ensured output voltage accuracy is 1% at room temperature.
  • Low Noise: Broadband output noise is only 18 µV (typical) with a 10-nF bypass capacitor.

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Technical documentation

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Type Title Date
* Datasheet LP3878-ADJ Micropower 800-mA Low-Noise "Ceramic Stable" Adjustable Voltage Regulator for 1-V to 5-V Applications datasheet (Rev. D) Feb. 09, 2015
Application note A Topical Index of TI LDO Application Notes (Rev. F) Jun. 27, 2019
Technical article LDO basics: capacitor vs. capacitance Aug. 01, 2018
Technical article LDO Basics: Preventing reverse current Jul. 25, 2018
Selection guide Power Management Guide 2018 (Rev. R) Jun. 25, 2018
Technical article LDO basics: introduction to quiescent current Jun. 20, 2018
Selection guide Low Dropout Regulators Quick Reference Guide (Rev. P) Mar. 21, 2018
Technical article LDO basics: noise – part 1 Jun. 14, 2017
User guide AN-1409 LP3878-ADJ Evaluation Board (Rev. D) Jun. 02, 2013
Application note AN-2145 Power Considerations for SDI Products (Rev. B) Apr. 26, 2013
Application note AN-2146 Power Design for SDI and Other Noise-Sensitive Devices (Rev. A) Apr. 26, 2013
Application note AN-1950 Silently Powering Low Noise Applications (Rev. A) Apr. 22, 2013
User guide High-IF Sub-sampling Receiver Subsystem User Guide Jan. 27, 2012
User guide SP16130CH4RB Low IF Receiver Reference Design User Guide Jan. 27, 2012
White paper Using Power to Improve Signal-Path Performance Aug. 01, 2006

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

document-generic User guide

The LP3878-ADJ is an 800 mA low-dropout linear regulator whose output voltage can be externally set to any value between 1V and 5.5 V using two resistors. This application note gives information about the evaluation board supplied to demonstrate the function of this part. This board is designed to (...)

  • 1.0V to 5.5V output
  • Designed for use with low ESR ceramic capicitors
  • Very low output noise
  • 8 lead PSOP and LLP surface mount package
  • <10µA quiescent current in shutdown
  • Low ground pin current at all loads
  • Over-temperature-current protection
  • -40°C to +125°C operating junction temperature range


  • ASIC (...)
document-generic User guide

The TSW16DX370EVM is a reference design board used to evaluate the high performance receiver IF super-heterodyne subsystem solution including the following products from Texas Instruments:

  • TRF37B32 dual down-converting mixer with integrated IF amplifier
  • LMH6521 dual digitally controlled variable gain (...)
  • High linearity, low noise Superheterodyne sub-system reference design
  • Wide RF input range and greater than 100MHz of IF bandwidth
  • Quickly evaluate ADC performance through High Speed Data Converter Pro software
  • Simple connection to TSW14J56EVM data capture card or direct connection to FMC based Xilinx (...)

Design tools & simulation

SNVMBD1A.ZIP (2 KB) - PSpice Model
SNVMBD2A.ZIP (669 KB) - PSpice Model
SNAC011.ZIP (3372 KB)
SNAC012.ZIP (3259 KB)

Reference designs

160-MHz Bandwidth Wireless Signal Tester Reference Design
TIDA-00988 — This reference design implements an IF subsystem for a standard wireless signal tester with an active balun-amplifier (LMH5401), LC bandpass filter, 16-bit ADC (ADC31JB68) and clock cleaner and generator PLL (LMK04828). Measurements using modulated signals demonstrate reception of the signal with (...)
document-generic Schematic document-generic User guide
RF Sampling 4-GSPS ADC Reference Design with 8-GHz DC-Coupled Differential Amplifier
TIDA-00431 Wideband radio frequency (RF) receivers allow greatly increased flexibility in radio designs. The wide instantaneous bandwidth allows flexible tuning without changing hardware and the ability to capture multiple channels at widely separated frequencies.

This reference design describes a wideband RF (...)

document-generic Schematic document-generic User guide
Low Noise Power Solution Reference Design for Clock Generators
TIDA-00597 The TIDA-00597 can provide very low noise output power for clock generator.
document-generic Schematic document-generic User guide
Linear Regulator as a Dynamic Voltage Scaling Power Supply Reference Design
TIDA-00531 The TIDA-00531 reference design features dynamic voltage scaling (DVS) as a power management solution to power CPU/DSP core voltages.
document-generic Schematic document-generic User guide
700–2700 MHz Dual-Channel Receiver with 16-Bit ADC and 100 MHz IF Bandwidth Reference Design
TIDA-00360 The increasing demand on wireless networks to provide faster data links to customers has driven transceiver hardware to increasingly demanding performance with enough bandwidth to support the largest standardized multi-carrier frequency bands (with band aggregation in some cases) and enough receiver (...)
document-generic Schematic document-generic User guide
Synchronization of JESD204B Giga-Sample ADCs using Xilinx Platform for Phased Array Radar Systems
TIDA-00432 This system level design shows how two ADC12J4000 evaluation modules (EVMs) can be synchronized together using a Xilinx VC707 platform. The design document describes the required hardware modifications and device configurations, including the clocking scheme. Example configuration files are shown (...)
document-generic Schematic document-generic User guide
Equalization Optimization of a JESD204B Serial Link Reference Design
TIDA-00353 Employing equalization techniques is an effective way of compensating for channel loss in JESD204B high speed serial interfaces for data converters. This reference design features the ADC16DX370, a dual 16-bit, 370 MSPS analog-to-digital converter (ADC) that utilizes de-emphasis equalization to (...)
document-generic Schematic document-generic User guide
JESD204B Link Latency Design Using a High Speed ADC
TIDA-00153 JESD204B links are the latest trend in data-converter digital interfaces. These links take advantage of high-speed serial-digital technology to offer many compelling benefits including improved channel densities. This reference design addresses one of the challenges of adopting the new interface (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
SO PowerPAD (DDA) 8 View options
WSON (NGT) 8 View options

Ordering & quality

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