SLLSFT3 November   2025 MC121-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings Auto
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Timing Requirements
    7. 5.7 Timing Diagrams
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Motor Control
        1. 6.3.1.1 Duty Input
        2. 6.3.1.2 Duty Curve
        3. 6.3.1.3 Motor Start, Speed Change, and Stop
        4. 6.3.1.4 Open-Loop (Duty Cycle) Control
        5. 6.3.1.5 Closed-Loop (Speed) Control
        6. 6.3.1.6 Commutation
          1. 6.3.1.6.1 Hall Sensor
            1. 6.3.1.6.1.1 Field Direction Definition
            2. 6.3.1.6.1.2 Internal Hall Latch Sensor Output
          2. 6.3.1.6.2 Hall Offset
          3. 6.3.1.6.3 Square Commutation
          4. 6.3.1.6.4 Soft Commutation
        7. 6.3.1.7 PWM Modulation Modes
      2. 6.3.2 Protections
        1. 6.3.2.1 Locked Rotor Protection
        2. 6.3.2.2 Current Limit
        3. 6.3.2.3 Overcurrent Protection (OCP)
        4. 6.3.2.4 VM Undervoltage Lockout (UVLO)
        5. 6.3.2.5 VM Over Voltage Protection (OVP)
        6. 6.3.2.6 Thermal Shutdown (TSD)
        7. 6.3.2.7 Integrated Supply (VM) Clamp
    4. 6.4 Device Functional Modes
      1. 6.4.1 Active Mode
      2. 6.4.2 Sleep and Standby Mode
      3. 6.4.3 Fault Mode
      4. 6.4.4 Test Mode and One-Time Programmable Memory
    5. 6.5 Programming
      1. 6.5.1 I2C Communication
        1. 6.5.1.1 I2C Read
        2. 6.5.1.2 I2C Write
  8. 7 Register Map
    1. 7.1 USR_OTP Registers
    2. 7.2 USR_TM Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 External Components
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Bulk Capacitance
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History

Package Options

Mechanical Data (Package|Pins)
  • DYM|6
  • DEZ|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.1.7 PWM Modulation Modes

The MC121-Q1 provides three PWM modulation modes: synchronous, asynchronous and hybrid. The PWM_MODE bit configures the PWM modulation mode. During synchronous mode, both low-side FETs turn on during the PWM OFF time. Synchronous mode reduces power loss by conducting the freewheeling current through the FET instead of the body diode. However, depending on turn-off current and motor winding inductance, there can be reverse current conduction during synchronous modulation resulting in negative torque and lower motor speed. During asynchronous mode, only one low-side FET remains on during the PWM OFF time while all other FETs are disabled and the freewheeling current is conducted through the body diode of a LS FET. In asynchronous mode, there is no reverse current flow during PWM off time but the power loss can be higher due to body diode conduction. Hybrid combines both modes - synchronous till the freewheeling current drops to < 13mA followed by asynchronous to prevent reverse current flow.

Table 6-1 shows the H-bridge states for the output PWM - H indicates HS FET in given OUTx leg is ON, L indicates LS FET in given OUTx leg is ON, Z indicates both FETs in given OUTx legs are in Hi-Z. The Hall offset signal is the internal signal determined from the Hall sensor state and device settings. The Hall offset signal determines the output switching states in the commutation algorithm state machine. The input PWM duty cycle and commutation mode (square/soft) determine the instantaneous output PWM duty cycle, DOUT.

Table 6-1 Output State Table
Driver State Description

Modulation mode set by PWM_MODE

 Hall Offset Signal OUT1 OUT2
DOUT PWM ON time/duty cycle X L L H
X H H L
(1-DOUT), Current Limiting, θDEMAG Motor current recirculation during PWM OFF time/duty or during current limiting off time, or phase demagnetization before a commutation event Asynchronous mode L L Z
H Z L
Synchronous mode X L L

Figure 6-19 shows the motor current flow through the H-bridge during PWM ON time, PWM OFF time, and demagnetization states. Refer to Section 6.3.1.6.3 for more details on demagnetization state.

MC121-Q1 Motor Current and Output States Figure 6-19 Motor Current and Output States

The hybrid PWM mode enables both low-side FETs during the PWM OFF time (same as synchronous mode) to avoid recirculating the motor current through the body diode. Once the motor current reaches <13mA, a zero-current detector disables the acceptable low-side FET to place the H-bridge in the asynchronous mode. By automatically switching between synchronous and asynchronous modes, the MC121-Q1 reduces device power loss while avoiding back EMF generating unintended negative current in the motor winding.

MC121-Q1 Asynchronous and Hybrid Modulation Figure 6-20 Asynchronous and Hybrid Modulation
MC121-Q1 Synchronous and Hybrid Modulation Figure 6-21 Synchronous and Hybrid Modulation

Table 6-2 shows the settings for the PWM_MODE bitfield to configure the PWM modulation mode.

Table 6-2 Modulation Mode with PWM_MODE
PWM_MODE Bits PWM and Current Limiting OFF Time Demagnetization State
000b Asynchronous Asynchronous
001b Asynchronous Synchronous
010b Synchronous Asynchronous
011b Synchronous Synchronous
100b Synchronous Hybrid
101b Asynchronous Hybrid
110b Hybrid Asynchronous
111b Hybrid Hybrid