1.4 Functional Block Diagram
Figure 1-1 shows the functional block diagram.
Figure 1-1 Functional Block Diagram
- The device has one main power pair of DVCC and DVSS that supplies both digital and analog modules. Recommended bypass and decoupling capacitors are 4.7 µF to 10 µF and 0.1 µF, respectively, with ±5% accuracy.
- P1 and P2 feature the pin-interrupt function and can wake the MCU from LPM3.5.
- Each Timer_A3 has three CC registers, but only the CCR1 and CCR2 are externally connected. CCR0 registers can only be used for internal period timing and interrupt generation.
- In LPM3.5, the RTC counter can be functional while the remaining peripherals are off.
- Not all I/Os are bonded in TSSOP-56 and TSSOP-48 packages (refer to Table 4-1). All I/Os can be configured as Capacitive Touch I/Os.