SLASE45E October   2014  – December 2019 MSP430FR2032 , MSP430FR2033

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
    3. 4.3 Pin Multiplexing
    4. 4.4 Connection of Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Active Mode Supply Current Per MHz
    6. 5.6  Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 5.7  Low-Power Mode LPM3 and LPM4 Supply Currents (Into VCC) Excluding External Current
    8. 5.8  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 5.9  Typical Characteristics, Low-Power Mode Supply Currents
    10. 5.10 Typical Characteristics - Current Consumption Per Module
    11. 5.11 Thermal Characteristics
    12. 5.12 Timing and Switching Characteristics
      1. 5.12.1 Power Supply Sequencing
        1. Table 5-1 PMM, SVS and BOR
      2. 5.12.2 Reset Timing
        1. Table 5-2 Wake-Up Times From Low-Power Modes and Reset
      3. 5.12.3 Clock Specifications
        1. Table 5-3 XT1 Crystal Oscillator (Low Frequency)
        2. Table 5-4 DCO FLL, Frequency
        3. Table 5-5 REFO
        4. Table 5-6 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. Table 5-7 Module Oscillator Clock (MODCLK)
      4. 5.12.4 Digital I/Os
        1. Table 5-8 Digital Inputs
        2. Table 5-9 Digital Outputs
        3. 5.12.4.1  Digital I/O Typical Characteristics
      5. 5.12.5 Timer_A
        1. Table 5-10 Timer_A Recommended Operating Conditions
      6. 5.12.6 eUSCI
        1. Table 5-11 eUSCI (UART Mode) Recommended Operating Conditions
        2. Table 5-12 eUSCI (UART Mode) Switching Characteristics
        3. Table 5-13 eUSCI (SPI Master Mode) Recommended Operating Conditions
        4. Table 5-14 eUSCI (SPI Master Mode) Switching Characteristics
        5. Table 5-15 eUSCI (SPI Slave Mode) Switching Characteristics
        6. Table 5-16 eUSCI (I2C Mode) Switching Characteristics
      7. 5.12.7 ADC
        1. Table 5-17 ADC, Power Supply and Input Range Conditions
        2. Table 5-18 ADC, 10-Bit Timing Parameters
        3. Table 5-19 ADC, 10-Bit Linearity Parameters
      8. 5.12.8 FRAM
        1. Table 5-20 FRAM
      9. 5.12.9 Emulation and Debug
        1. Table 5-21 JTAG and Spy-Bi-Wire Interface Characteristics
  6. 6Detailed Description
    1. 6.1  CPU
    2. 6.2  Operating Modes
    3. 6.3  Interrupt Vector Addresses
    4. 6.4  Bootloader (BSL)
    5. 6.5  JTAG Standard Interface
    6. 6.6  Spy-Bi-Wire Interface (SBW)
    7. 6.7  FRAM
    8. 6.8  Memory Protection
    9. 6.9  Peripherals
      1. 6.9.1  Power Management Module (PMM) and On-chip Reference Voltages
      2. 6.9.2  Clock System (CS) and Clock Distribution
      3. 6.9.3  General-Purpose Input/Output Port (I/O)
      4. 6.9.4  Watchdog Timer (WDT)
      5. 6.9.5  System Module (SYS)
      6. 6.9.6  Cyclic Redundancy Check (CRC)
      7. 6.9.7  Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
      8. 6.9.8  Timers (Timer0_A3, Timer1_A3)
      9. 6.9.9  Real-Time Clock (RTC) Counter
      10. 6.9.10 10-Bit Analog Digital Converter (ADC)
      11. 6.9.11 Embedded Emulation Module (EEM)
      12. 6.9.12 Input/Output Diagrams
        1. 6.9.12.1  Port P1 Input/Output With Schmitt Trigger
        2. 6.9.12.2  Port P2 Input/Output With Schmitt Trigger
        3. 6.9.12.3  Port P3 Input/Output With Schmitt Trigger
        4. 6.9.12.4  Port P4.0 Input/Output With Schmitt Trigger
        5. 6.9.12.5  Port P4.1 and P4.2 Input/Output With Schmitt Trigger
        6. 6.9.12.6  Port 4.3, P4.4, P4.5, P4.6, and P4.7 Input/Output With Schmitt Trigger
        7. 6.9.12.7  Port P5.0, P5.1, P5.2, and P5.3 Input/Output With Schmitt Trigger
        8. 6.9.12.8  Port P5.4, P5.5, P5.6, and P5.7 Input/Output With Schmitt Trigger
        9. 6.9.12.9  Port P6.0, P6.1, P6.2, and P6.3 Input/Output With Schmitt Trigger
        10. 6.9.12.10 Port P6.4, P6.5, P6.6, and P6.7 Input/Output With Schmitt Trigger
        11. 6.9.12.11 Port P7.0, P7.1, P7.2, and P7.3 Input/Output With Schmitt Trigger
        12. 6.9.12.12 Port P7.4, P7.5, P7.6, and P7.7 Input/Output With Schmitt Trigger
        13. 6.9.12.13 Port P8.0 and P8.1 Input/Output With Schmitt Trigger
        14. 6.9.12.14 Port P8.2 and P8.3 Input/Output With Schmitt Trigger
    10. 6.10 Device Descriptors (TLV)
    11. 6.11 Memory
      1. 6.11.1 Peripheral File Map
    12. 6.12 Identification
      1. 6.12.1 Revision Identification
      2. 6.12.2 Device Identification
      3. 6.12.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 General Layout Recommendations
      7. 7.1.7 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Layout Guidelines
  8. 8Device and Documentation Support
    1. 8.1 Getting Started
    2. 8.2 Device Nomenclature
    3. 8.3 Tools and Sofware
    4. 8.4 Documentation Support
    5. 8.5 Related Links
    6. 8.6 Community Resources
    7. 8.7 Trademarks
    8. 8.8 Electrostatic Discharge Caution
    9. 8.9 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.11.1 Peripheral File Map

Table 6-31 shows the base address and the memory size of the register region for each peripheral, and Table 6-32 through Table 6-50 show all of the available registers for each peripheral and their address offsets.

Table 6-31 Peripherals Summary

MODULE NAME BASE ADDRESS SIZE REGISTERS
Special Functions 0100h 0010h Table 6-32
PMM 0120h 0020h Table 6-33
SYS 0140h 0030h Table 6-34
CS 0180h 0020h Table 6-35
FRAM 01A0h 0010h Table 6-36
CRC 01C0h 0008h Table 6-37
WDT 01CCh 0002h Table 6-38
Port P1, P2 0200h 0020h Table 6-39
Port P3, P4 0220h 0020h Table 6-40
Port P5, P6 0240h 0020h Table 6-41
Port P7, P8 0260h 0020h Table 6-42
Capacitive Touch I/O 02E0h 0010h Table 6-43
Timer0_A3 0300h 0030h Table 6-44
Timer1_A3 0340h 0030h Table 6-45
RTC 03C0h 0010h Table 6-46
eUSCI_A0 0500h 0020h Table 6-47
eUSCI_B0 0540h 0030h Table 6-48
Backup Memory 0660h 0020h Table 6-49
ADC 0700h 0040h Table 6-50

Table 6-32 Special Function Registers (Base Address: 0100h)

REGISTER DESCRIPTION REGISTER OFFSET
SFR interrupt enable SFRIE1 00h
SFR interrupt flag SFRIFG1 02h
SFR reset pin control SFRRPCR 04h

Table 6-33 PMM Registers (Base Address: 0120h)

REGISTER DESCRIPTION REGISTER OFFSET
PMM control 0 PMMCTL0 00h
PMM control 1 PMMCTL1 02h
PMM control 2 PMMCTL2 04h
PMM interrupt flags PMMIFG 0Ah
PM5 control 0 PM5CTL0 10h

Table 6-34 SYS Registers (Base Address: 0140h)

REGISTER DESCRIPTION REGISTER OFFSET
System control SYSCTL 00h
Bootloader configuration area SYSBSLC 02h
JTAG mailbox control SYSJMBC 06h
JTAG mailbox input 0 SYSJMBI0 08h
JTAG mailbox input 1 SYSJMBI1 0Ah
JTAG mailbox output 0 SYSJMBO0 0Ch
JTAG mailbox output 1 SYSJMBO1 0Eh
Bus Error vector generator SYSBERRIV 18h
User NMI vector generator SYSUNIV 1Ah
System NMI vector generator SYSSNIV 1Ch
Reset vector generator SYSRSTIV 1Eh
System configuration 0 SYSCFG0 20h
System configuration 1 SYSCFG1 22h
System configuration 2 SYSCFG2 24h

Table 6-35 CS Registers (Base Address: 0180h)

REGISTER DESCRIPTION REGISTER OFFSET
CS control register 0 CSCTL0 00h
CS control register 1 CSCTL1 02h
CS control register 2 CSCTL2 04h
CS control register 3 CSCTL3 06h
CS control register 4 CSCTL4 08h
CS control register 5 CSCTL5 0Ah
CS control register 6 CSCTL6 0Ch
CS control register 7 CSCTL7 0Eh
CS control register 8 CSCTL8 10h

Table 6-36 FRAM Registers (Base Address: 01A0h)

REGISTER DESCRIPTION REGISTER OFFSET
FRAM control 0 FRCTL0 00h
General control 0 GCCTL0 04h
General control 1 GCCTL1 06h

Table 6-37 CRC Registers (Base Address: 01C0h)

REGISTER DESCRIPTION REGISTER OFFSET
CRC data input CRC16DI 00h
CRC data input reverse byte CRCDIRB 02h
CRC initialization and result CRCINIRES 04h
CRC result reverse byte CRCRESR 06h

Table 6-38 WDT Registers (Base Address: 01CCh)

REGISTER DESCRIPTION REGISTER OFFSET
Watchdog timer control WDTCTL 00h

Table 6-39 Port P1, P2 Registers (Base Address: 0200h)

REGISTER DESCRIPTION REGISTER OFFSET
Port P1 input P1IN 00h
Port P1 output P1OUT 02h
Port P1 direction P1DIR 04h
Port P1 pulling register enable P1REN 06h
Port P1 selection 0 P1SEL0 0Ah
Port P1 interrupt vector word P1IV 0Eh
Port P1 interrupt edge select P1IES 18h
Port P1 interrupt enable P1IE 1Ah
Port P1 interrupt flag P1IFG 1Ch
Port P2 input P2IN 01h
Port P2 output P2OUT 03h
Port P2 direction P2DIR 05h
Port P2 pulling register enable P2REN 07h
Port P2 selection 0(1) P2SEL0 0Bh
Port P2 interrupt vector word P2IV 1Eh
Port P2 interrupt edge select P2IES 19h
Port P2 interrupt enable P2IE 1Bh
Port P2 interrupt flag P2IFG 1Dh
(1) Port P2 selection register does not feature any valid bits. P2SEL0 presents for 16-bit Port A operation with P1SEL0.

Table 6-40 Port P3, P4 Registers (Base Address: 0220h)

REGISTER DESCRIPTION REGISTER OFFSET
Port P3 input P3IN 00h
Port P3 output P3OUT 02h
Port P3 direction P3DIR 04h
Port P3 pulling register enable P3REN 06h
Port P3 selection 0(1) P3SEL0 0Ah
Port P4 input P4IN 01h
Port P4 output P4OUT 03h
Port P4 direction P4DIR 05h
Port P4 pulling register enable P4REN 07h
Port P4 selection 0 P4SEL0 0Bh
(1) Port P3 selection register does not feature any valid bits. P3SEL0 presents for 16-bit Port B operation with P4SEL0.

Table 6-41 Port P5, P6 Registers (Base Address: 0240h)

REGISTER DESCRIPTION REGISTER OFFSET
Port P5 input P5IN 00h
Port P5 output P5OUT 02h
Port P5 direction P5DIR 04h
Port P5 pulling register enable P5REN 06h
Port P5 selection 0 P5SEL0 0Ah
Port P6 input P6IN 01h
Port P6 output P6OUT 03h
Port P6 direction P6DIR 05h
Port P6 pulling register enable P6REN 07h
Port P6 selection 0(1) P6SEL0 0Bh
(1) Port P6 selection register does not feature any valid bits. P6SEL0 presents for 16-bit Port C operation with P5SEL0.

Table 6-42 Port P7, P8 Registers (Base Address: 0260h)

REGISTER DESCRIPTION REGISTER OFFSET
Port P7 input P7IN 00h
Port P7 output P7OUT 02h
Port P7 direction P7DIR 04h
Port P7 pulling register enable P7REN 06h
Port P7 selection 0(1) P7SEL0 0Ah
Port P8 input P8IN 01h
Port P8 output P8OUT 03h
Port P8 direction P8DIR 05h
Port P8 pulling register enable P8REN 07h
Port P8 selection 0 P8SEL0 0Bh
(1) Port P7 selection register does not feature any valid bits. P7SEL0 presents for 16-bit Port D operation with P8SEL0.

Table 6-43 Capacitive Touch I/O Registers (Base Address: 02E0h)

REGISTER DESCRIPTION REGISTER OFFSET
Capacitive Touch I/O 0 control CAPTIO0CTL 0Eh

Table 6-44 Timer0_A3 Registers (Base Address: 0300h)

REGISTER DESCRIPTION REGISTER OFFSET
TA0 control TA0CTL 00h
Capture/compare control 0 TA0CCTL0 02h
Capture/compare control 1 TA0CCTL1 04h
Capture/compare control 2 TA0CCTL2 06h
TA0 counter register TA0R 10h
Capture/compare register 0 TA0CCR0 12h
Capture/compare register 1 TA0CCR1 14h
Capture/compare register 2 TA0CCR2 16h
TA0 expansion register 0 TA0EX0 20h
TA0 interrupt vector TA0IV 2Eh

Table 6-45 Timer1_A3 Registers (Base Address: 0340h)

REGISTER DESCRIPTION REGISTER OFFSET
TA1 control TA1CTL 00h
Capture/compare control 0 TA1CCTL0 02h
Capture/compare control 1 TA1CCTL1 04h
Capture/compare control 2 TA1CCTL2 06h
TA1 counter register TA1R 10h
Capture/compare register 0 TA1CCR0 12h
Capture/compare register 1 TA1CCR1 14h
Capture/compare register 2 TA1CCR2 16h
TA1 expansion register 0 TA1EX0 20h
TA1 interrupt vector TA1IV 2Eh

Table 6-46 RTC Registers (Base Address: 03C0h)

REGISTER DESCRIPTION REGISTER OFFSET
RTC control RTCCTL 00h
RTC interrupt vector RTCIV 04h
RTC modulo RTCMOD 08h
RTC counter RTCCNT 0Ch

Table 6-47 eUSCI_A0 Registers (Base Address: 0500h)

REGISTER DESCRIPTION REGISTER OFFSET
eUSCI_A control word 0 UCA0CTLW0 00h
eUSCI_A control word 1 UCA0CTLW1 02h
eUSCI_A control rate 0 UCA0BR0 06h
eUSCI_A control rate 1 UCA0BR1 07h
eUSCI_A modulation control UCA0MCTLW 08h
eUSCI_A status UCA0STAT 0Ah
eUSCI_A receive buffer UCA0RXBUF 0Ch
eUSCI_A transmit buffer UCA0TXBUF 0Eh
eUSCI_A LIN control UCA0ABCTL 10h
eUSCI_A IrDA transmit control lUCA0IRTCTL 12h
eUSCI_A IrDA receive control IUCA0IRRCTL 13h
eUSCI_A interrupt enable UCA0IE 1Ah
eUSCI_A interrupt flags UCA0IFG 1Ch
eUSCI_A interrupt vector word UCA0IV 1Eh

Table 6-48 eUSCI_B0 Registers (Base Address: 0540h)

REGISTER DESCRIPTION REGISTER OFFSET
eUSCI_B control word 0 UCB0CTLW0 00h
eUSCI_B control word 1 UCB0CTLW1 02h
eUSCI_B bit rate 0 UCB0BR0 06h
eUSCI_B bit rate 1 UCB0BR1 07h
eUSCI_B status word UCB0STATW 08h
eUSCI_B byte counter threshold UCB0TBCNT 0Ah
eUSCI_B receive buffer UCB0RXBUF 0Ch
eUSCI_B transmit buffer UCB0TXBUF 0Eh
eUSCI_B I2C own address 0 UCB0I2COA0 14h
eUSCI_B I2C own address 1 UCB0I2COA1 16h
eUSCI_B I2C own address 2 UCB0I2COA2 18h
eUSCI_B I2C own address 3 UCB0I2COA3 1Ah
eUSCI_B receive address UCB0ADDRX 1Ch
eUSCI_B address mask UCB0ADDMASK 1Eh
eUSCI_B I2C slave address UCB0I2CSA 20h
eUSCI_B interrupt enable UCB0IE 2Ah
eUSCI_B interrupt flags UCB0IFG 2Ch
eUSCI_B interrupt vector word UCB0IV 2Eh

Table 6-49 Backup Memory Registers (Base Address: 0660h)

REGISTER DESCRIPTION REGISTER OFFSET
Backup Memory 0 BAKMEM0 00h
Backup Memory 1 BAKMEM1 02h
Backup Memory 2 BAKMEM2 04h
Backup Memory 3 BAKMEM3 06h
Backup Memory 4 BAKMEM4 08h
Backup Memory 5 BAKMEM5 0Ah
Backup Memory 6 BAKMEM6 0Ch
Backup Memory 7 BAKMEM7 0Eh
Backup Memory 8 BAKMEM8 10h
Backup Memory 9 BAKMEM9 12h
Backup Memory 10 BAKMEM10 14h
Backup Memory 11 BAKMEM11 16h
Backup Memory 12 BAKMEM12 18h
Backup Memory 13 BAKMEM13 1Ah
Backup Memory 14 BAKMEM14 1Ch
Backup Memory 15 BAKMEM15 1Eh

Table 6-50 ADC Registers (Base Address: 0700h)

REGISTER DESCRIPTION REGISTER OFFSET
ADC control register 0 ADCCTL0 00h
ADC control register 1 ADCCTL1 02h
ADC control register 2 ADCCTL2 04h
ADC window comparator low threshold ADCLO 06h
ADC window comparator high threshold ADCHI 08h
ADC memory control register 0 ADCMCTL0 0Ah
ADC conversion memory register ADCMEM0 12h
ADC interrupt enable ADCIE 1Ah
ADC interrupt flags ADCIFG 1Ch
ADC interrupt vector word ADCIV 1Eh