SLASEV3A March   2020  – December 2020 MSP430FR6005 , MSP430FR6007

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Functional Block Diagram
  5. Revision History
  6. Device Comparison
    1. 6.1 Related Products
  7. Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Pin Attributes
    3. 7.3 Signal Descriptions
    4. 7.4 Pin Multiplexing
    5. 7.5 Buffer Type
    6. 7.6 Connection of Unused Pins
  8. Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Typical Characteristics, Active Mode Supply Currents
    6. 8.6  Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
    7. 8.7  Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 8.8  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    9. 8.9  Low-Power Mode (LPMx.5) Supply Currents (Into VCC) Excluding External Current
    10. 8.10 Typical Characteristics, Low-Power Mode Supply Currents
    11. 8.11 Current Consumption per Module
    12. 8.12 Thermal Resistance Characteristics for 100-Pin LQFP (PZ) Package
    13. 8.13 Timing and Switching Characteristics
      1. 8.13.1  Power Supply Sequencing
        1. 8.13.1.1 Brownout and Device Reset Power Ramp Requirements
        2. 8.13.1.2 SVS
      2. 8.13.2  Reset Timing
        1. 8.13.2.1 Reset Input
      3. 8.13.3  Clock Specifications
        1. 8.13.3.1 Low-Frequency Crystal Oscillator, LFXT
        2. 8.13.3.2 High-Frequency Crystal Oscillator, HFXT
        3. 8.13.3.3 DCO
        4. 8.13.3.4 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. 8.13.3.5 Module Oscillator (MODOSC)
      4. 8.13.4  Wake-up Characteristics
        1. 8.13.4.1 Wake-up Times From Low-Power Modes and Reset
        2. 8.13.4.2 Typical Wake-up Charges
        3. 8.13.4.3 Typical Characteristics, Average LPM Currents vs Wake-up Frequency
      5. 8.13.5  Digital I/Os
        1. 8.13.5.1 Digital Inputs
        2. 8.13.5.2 Digital Outputs
        3. 8.13.5.3 Typical Characteristics, Digital Outputs
      6. 8.13.6  LEA
        1. 8.13.6.1 Low-Energy Accelerator (LEA) Performance
      7. 8.13.7  Timer_A and Timer_B
        1. 8.13.7.1 Timer_A
        2. 8.13.7.2 Timer_B
      8. 8.13.8  eUSCI
        1. 8.13.8.1 eUSCI (UART Mode) Clock Frequency
        2. 8.13.8.2 eUSCI (UART Mode) Switching Characteristics
        3. 8.13.8.3 eUSCI (SPI Master Mode) Clock Frequency
        4. 8.13.8.4 eUSCI (SPI Master Mode) Switching Characteristics
        5. 8.13.8.5 eUSCI (SPI Master Mode) Timing Diagrams
        6. 8.13.8.6 eUSCI (SPI Slave Mode) Switching Characteristics
        7. 8.13.8.7 eUSCI (SPI Slave Mode) Timing Diagrams
        8. 8.13.8.8 eUSCI (I2C Mode) Switching Characteristics
        9. 8.13.8.9 eUSCI (I2C Mode) Timing Diagram
      9. 8.13.9  Segment LCD Controller
        1. 8.13.9.1 LCD_C Recommended Operating Conditions
        2. 8.13.9.2 LCD_C Electrical Characteristics
      10. 8.13.10 ADC12_B
        1. 8.13.10.1 12-Bit ADC, Power Supply and Input Range Conditions
        2. 8.13.10.2 12-Bit ADC, Timing Parameters
        3. 8.13.10.3 12-Bit ADC, Linearity Parameters
        4. 8.13.10.4 12-Bit ADC, Dynamic Performance With External Reference
        5. 8.13.10.5 12-Bit ADC, Dynamic Performance With Internal Reference
        6. 8.13.10.6 12-Bit ADC, Temperature Sensor and Built-In V1/2
        7. 8.13.10.7 12-Bit ADC, External Reference
      11. 8.13.11 Reference
        1. 8.13.11.1 REF, Built-In Reference
      12. 8.13.12 Comparator
        1. 8.13.12.1 Comparator_E
      13. 8.13.13 FRAM
        1. 8.13.13.1 FRAM
      14. 8.13.14 USS
        1. 8.13.14.1 USS Recommended Operating Conditions
        2. 8.13.14.2 USS LDO
        3. 8.13.14.3 USSXTAL
        4. 8.13.14.4 USS HSPLL
        5. 8.13.14.5 USS SDHS
        6. 8.13.14.6 USS PHY Output Stage
        7. 8.13.14.7 USS PHY Input Stage, Multiplexer
        8. 8.13.14.8 USS PGA
        9. 8.13.14.9 USS Bias Voltage Generator
      15. 8.13.15 Emulation and Debug
        1. 8.13.15.1 JTAG and Spy-Bi-Wire Interface
  9. Detailed Description
    1. 9.1  Overview
    2. 9.2  CPU
    3. 9.3  Ultrasonic Sensing Solution (USS) Module
    4. 9.4  Low-Energy Accelerator (LEA) for Signal Processing
    5. 9.5  Operating Modes
      1. 9.5.1 Peripherals in Low-Power Modes
      2. 9.5.2 Idle Currents of Peripherals in LPM3 and LPM4
    6. 9.6  Interrupt Vector Table and Signatures
    7. 9.7  Bootloader (BSL)
    8. 9.8  JTAG Operation
      1. 9.8.1 JTAG Standard Interface
      2. 9.8.2 Spy-Bi-Wire (SBW) Interface
    9. 9.9  FRAM Controller A (FRCTL_A)
    10. 9.10 RAM
    11. 9.11 Tiny RAM
    12. 9.12 Memory Protection Unit (MPU) Including IP Encapsulation
    13. 9.13 Peripherals
      1. 9.13.1  Digital I/O
      2. 9.13.2  Oscillator and Clock System (CS)
      3. 9.13.3  Power-Management Module (PMM)
      4. 9.13.4  Hardware Multiplier (MPY)
      5. 9.13.5  Real-Time Clock (RTC_C)
      6. 9.13.6  Watchdog Timer (WDT_A)
      7. 9.13.7  System Module (SYS)
      8. 9.13.8  DMA Controller
      9. 9.13.9  Enhanced Universal Serial Communication Interface (eUSCI)
      10. 9.13.10 TA0, TA1, and TA4
      11. 9.13.11 TA2 and TA3
      12. 9.13.12 TB0
      13. 9.13.13 ADC12_B
      14. 9.13.14 USS
      15. 9.13.15 Comparator_E
      16. 9.13.16 CRC16
      17. 9.13.17 CRC32
      18. 9.13.18 AES256 Accelerator
      19. 9.13.19 True Random Seed
      20. 9.13.20 Shared Reference (REF)
      21. 9.13.21 LCD_C
      22. 9.13.22 Embedded Emulation
        1. 9.13.22.1 Embedded Emulation Module (EEM) (S Version)
        2. 9.13.22.2 EnergyTrace++ Technology
    14. 9.14 Input/Output Diagrams
      1. 9.14.1  Port Function Select Registers (PySEL1 , PySEL0)
      2. 9.14.2  Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger
      3. 9.14.3  Port P1 (P1.2 to P1.7) Input/Output With Schmitt Trigger
      4. 9.14.4  Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger
      5. 9.14.5  Port P2 (P2.4 to P2.7) Input/Output With Schmitt Trigger
      6. 9.14.6  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      7. 9.14.7  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      8. 9.14.8  Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
      9. 9.14.9  Port P6 (P6.0) Input/Output With Schmitt Trigger
      10. 9.14.10 Port P6 (P6.1 to P6.5) Input/Output With Schmitt Trigger
      11. 9.14.11 Port P6 (P6.6 and P6.7) Input/Output With Schmitt Trigger
      12. 9.14.12 Port P7 (P7.0 to P7.3) Input/Output With Schmitt Trigger
      13. 9.14.13 Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger
      14. 9.14.14 Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger
      15. 9.14.15 Port P8 (P8.4 to P8.7) Input/Output With Schmitt Trigger
      16. 9.14.16 Port P9 (P9.0 to P9.3) Input/Output With Schmitt Trigger
      17. 9.14.17 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
      18. 9.14.18 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
      19. 9.14.19 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
    15. 9.15 Device Descriptors (TLV)
    16. 9.16 Memory Map
      1. 9.16.1 Peripheral File Map
    17. 9.17 Identification
      1. 9.17.1 Revision Identification
      2. 9.17.2 Device Identification
      3. 9.17.3 JTAG Identification
  10. 10Applications, Implementation, and Layout
    1. 10.1 Device Connection and Layout Fundamentals
      1. 10.1.1  Power Supply Decoupling and Bulk Capacitors
      2. 10.1.2  External Oscillator (HFXT and LFXT)
      3. 10.1.3  USS Oscillator (USSXT)
      4. 10.1.4  Transducer Connection to the USS Module
      5. 10.1.5  Charge Pump Control of Input Multiplexer
      6. 10.1.6  JTAG
      7. 10.1.7  Reset
      8. 10.1.8  Unused Pins
      9. 10.1.9  General Layout Recommendations
      10. 10.1.10 Do's and Don'ts
    2. 10.2 Peripheral- and Interface-Specific Design Information
      1. 10.2.1 ADC12_B Peripheral
        1. 10.2.1.1 Partial Schematic
        2. 10.2.1.2 Design Requirements
        3. 10.2.1.3 Detailed Design Procedure
        4. 10.2.1.4 Layout Guidelines
      2. 10.2.2 LCD_C Peripheral
        1. 10.2.2.1 Partial Schematic
        2. 10.2.2.2 Design Requirements
        3. 10.2.2.3 Detailed Design Procedure
        4. 10.2.2.4 Layout Guidelines
  11. 11Device and Documentation Support
    1. 11.1 Getting Started and Next Steps
    2. 11.2 Device Nomenclature
    3. 11.3 Tools and Software
    4. 11.4 Documentation Support
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Export Control Notice
    9. 11.9 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Attributes

Table 7-1 lists the attributes of each pin.

Table 7-1 Pin Attributes
PIN NUMBERSIGNAL NAME(1)(4)SIGNAL TYPE(2)BUFFER TYPE(3)POWER SOURCE(5)RESET STATE AFTER BOR(7)
1P2.2I/OLVCMOSDVCCOFF
COUTOLVCMOSDVCC
UCA0CLKI/OLVCMOSDVCC
A14IAnalogDVCC
C14IAnalogDVCC
2P2.3I/OLVCMOSDVCCOFF
TA0.0I/OLVCMOSDVCC
UCA0STEI/OLVCMOSDVCC
A15IAnalogDVCC
C15IAnalogDVCC
3P1.0I/OLVCMOSDVCCOFF
UCA1CLKI/OLVCMOSDVCC
TA1.0I/OLVCMOSDVCC
A0IAnalogDVCC
C0IAnalogDVCC
VREF-OAnalogDVCC
VeREF-IAnalogDVCC
4P1.1I/OLVCMOSDVCCOFF
UCA1STEI/OLVCMOSDVCC
TA4.0I/OLVCMOSDVCC
A1IAnalogDVCC
C1IAnalogDVCC
VREF+OAnalogDVCC
VeREF+IAnalogDVCC
5AVSS2PPowerN/A
6PJ.4I/OLVCMOSDVCCOFF
LFXINIAnalogDVCC
7PJ.5I/OLVCMOSDVCCOFF
LFXOUTOAnalogDVCC
8AVSS3PPowerN/A
9PJ.6I/OLVCMOSDVCC
HFXINIAnalogDVCC
10PJ.7I/OLVCMOSDVCCOFF
HFXOUTOAnalogDVCC
11AVSS4PPowerN/A
12P1.4I/OLVCMOSDVCCOFF
TB0.4I/OLVCMOSDVCC
UCB0STEI/OLVCMOSDVCC
A2IAnalogDVCC
C2IAnalogDVCC
13P1.5I/OLVCMOSDVCCOFF
TB0.5I/OLVCMOSDVCC
UCB0CLKI/OLVCMOSDVCC
A3IAnalogDVCC
C3IAnalogDVCC
14P1.6I/OLVCMOSDVCCOFF
UCB0SIMOI/OLVCMOSDVCC
UCB0SDAI/OLVCMOSDVCC
A4IAnalogDVCC
C4IAnalogDVCC
15P1.7I/OLVCMOSDVCCOFF
USSTRGILVCMOSDVCC
UCB0SOMII/OLVCMOSDVCC
UCB0SCLI/OLVCMOSDVCC
A5IAnalogDVCC
C5IAnalogDVCC
16P2.0I/OLVCMOSDVCCOFF
UCA0TXDOLVCMOSDVCC
UCA0SIMOI/OLVCMOSDVCC
A6IAnalogDVCC
C6IAnalogDVCC
17P2.1I/OLVCMOSDVCCOFF
UCA0RXDILVCMOSDVCC
UCA0SOMII/OLVCMOSDVCC
A7IAnalogDVCC
C7IAnalogDVCC
18P1.2I/OLVCMOSDVCCOFF
UCA1TXDOLVCMOSDVCC
UCA1SIMOI/OLVCMOSDVCC
A8IAnalogDVCC
C8IAnalogDVCC
19P1.3I/OLVCMOSDVCCOFF
UCA1RXDILVCMOSDVCC
UCA1SOMII/OLVCMOSDVCC
A9IAnalogDVCC
C9IAnalogDVCC
20TESTILVCMOSDVCCPD
SBWTCKILVCMOSDVCC
21RSTI/OLVCMOSDVCCPU
NMIILVCMOSDVCC
SBWTDIOI/OLVCMOSDVCC
22PJ.0I/OLVCMOSDVCCOFF
TDOOLVCMOSDVCC
ACLKOLVCMOSDVCC
SRSCG1OLVCMOSDVCC
DMAE0ILVCMOSDVCC
C10IAnalogDVCC
23PJ.1I/OLVCMOSDVCCOFF
TDIILVCMOSDVCC
TCLKILVCMOSDVCC
SMCLKOLVCMOSDVCC
SRSCG0OLVCMOSDVCC
TA4CLKILVCMOSDVCC
C11IAnalogDVCC
24PJ.2I/OLVCMOSDVCCOFF
TMSILVCMOSDVCC
MCLKOLVCMOSDVCC
SROSCOFFOLVCMOSDVCC
TB0OUTHILVCMOSDVCC
C12IAnalogDVCC
25PJ.3I/OLVCMOSDVCCOFF
TCKILVCMOSDVCC
RTCCLKOLVCMOSDVCC
SRCPUOFFOLVCMOSDVCC
TB0.6I/OLVCMOSDVCC
C13IAnalogDVCC
26DVSS1PPowerN/A
27DVCC1PPowerN/A
28P2.4I/OLVCMOSDVCCOFF
TA0CLKILVCMOSDVCC
TB0CLKILVCMOSDVCC
TA1CLKILVCMOSDVCC
S32OAnalogDVCC
29P2.5I/OLVCMOSDVCCOFF
TA4.0I/OLVCMOSDVCC
S31OAnalogDVCC
30P2.6I/OLVCMOSDVCCOFF
TA4.1I/OLVCMOSDVCC
S30OAnalogDVCC
31P3.0I/OLVCMOSDVCCOFF
TB0.0I/OLVCMOSDVCC
S29OAnalogDVCC
32P3.1I/OLVCMOSDVCCOFF
TB0.1OLVCMOSDVCC
S28OAnalogDVCC
33P3.2I/OLVCMOSDVCCOFF
TB0.2OLVCMOSDVCC
S27OAnalogDVCC
34P3.3I/OLVCMOSDVCCOFF
TB0.3I/OLVCMOSDVCC
S26OAnalogDVCC
35P3.4I/OLVCMOSDVCCOFF
TB0OUTHILVCMOSDVCC
S25OAnalogDVCC
36P3.5I/OLVCMOSDVCCOFF
TB0.4I/OLVCMOSDVCC
S24OAnalogDVCC
37P3.6I/OLVCMOSDVCCOFF
TB0.5I/OLVCMOSDVCC
S23OAnalogDVCC
38P3.7I/OLVCMOSDVCCOFF
TB0.6I/OLVCMOSDVCC
S22OAnalogDVCC
39P2.7I/OLVCMOSDVCCOFF
TA0.0I/OLVCMOSDVCC
S21OAnalogDVCC
40P9.0I/OLVCMOSDVCCOFF
TA1.0I/OLVCMOSDVCC
S20OAnalogDVCC
41P9.1I/OLVCMOSDVCCOFF
SMCLKOLVCMOSDVCC
S19OAnalogDVCC
42P9.2I/OLVCMOSDVCCOFF
MCLKOLVCMOSDVCC
S18OAnalogDVCC
43P9.3I/OLVCMOSDVCCOFF
ACLKOLVCMOSDVCC
S17OAnalogDVCC
44P4.0I/OLVCMOSDVCCOFF
RTCCLKOLVCMOSDVCC
S16OAnalogDVCC
45P4.1I/OLVCMOSDVCCOFF
UCA0CLKI/OLVCMOSDVCC
S15OAnalogDVCC
46P4.2I/OLVCMOSDVCCOFF
UCA0STEI/OLVCMOSDVCC
S14OAnalogDVCC
47P4.3I/OLVCMOSDVCCOFF
UCA0TXDOLVCMOSDVCC
UCA0SIMOI/OLVCMOSDVCC
S13OAnalogDVCC
48P4.4I/OLVCMOSDVCCOFF
UCA0RXDILVCMOSDVCC
UCA0SOMII/OLVCMOSDVCC
S12OAnalogDVCC
49P4.5I/OLVCMOSDVCCOFF
TA0CLKILVCMOSDVCC
TA1CLKILVCMOSDVCC
S11OAnalogDVCC
50P4.6I/OLVCMOSDVCCOFF
TB0CLKILVCMOSDVCC
TA4CLKILVCMOSDVCC
S10OAnalogDVCC
51DVSS2PPowerN/A
52DVCC2PPowerN/A
53P4.7I/OLVCMOSDVCCOFF
DMAE0ILVCMOSDVCC
S9OAnalogDVCC
54P5.0I/OLVCMOSDVCCOFF
UCA2TXDOLVCMOSDVCC
UCA2SIMOI/OLVCMOSDVCC
S8OAnalogDVCC
55P5.1I/OLVCMOSDVCCOFF
UCA2RXDILVCMOSDVCC
UCA2SOMII/OLVCMOSDVCC
S7OAnalogDVCC
56P5.2I/OLVCMOSDVCCOFF
UCA2CLKI/OLVCMOSDVCC
S6OAnalogDVCC
57P5.3I/OLVCMOSDVCCOFF
UCA2STEI/OLVCMOSDVCC
S5OAnalogDVCC
58P5.4I/OLVCMOSDVCCOFF
UCB1CLKI/OLVCMOSDVCC
S4OAnalogDVCC
59P5.5I/OLVCMOSDVCCOFF
TA0CLKILVCMOSDVCC
UCB1SIMOI/OLVCMOSDVCC
UCB1SDAI/OLVCMOSDVCC
S3OAnalogDVCC
60P5.6I/OLVCMOSDVCCOFF
UCB1SOMII/OLVCMOSDVCC
UCB1SCLI/OLVCMOSDVCC
S2OAnalogDVCC
61P5.7I/OLVCMOSDVCCOFF
UCB1STEI/OLVCMOSDVCC
S1OAnalogDVCC
62P6.0I/OLVCMOSDVCCOFF
COUTILVCMOSDVCC
S0OAnalogDVCC
63P6.4I/OLVCMOSDVCCOFF
COM0OAnalogDVCC
64P6.5I/OLVCMOSDVCCOFF
COM1OAnalogDVCC
65P6.6I/OLVCMOSDVCCOFF
COM2OAnalogDVCC
S38OAnalogDVCC
66P6.7I/OLVCMOSDVCCOFF
COM3OAnalogDVCC
S37OAnalogDVCC
67P7.0I/OLVCMOSDVCCOFF
UCA2TXDOLVCMOSDVCC
UCA2SIMOI/OLVCMOSDVCC
ACLKOLVCMOSDVCC
COM4OAnalogDVCC
S36OAnalogDVCC
68P7.1I/OLVCMOSDVCCOFF
UCA2RXDILVCMOSDVCC
UCA2SOMII/OLVCMOSDVCC
SMCLKOLVCMOSDVCC
COM5OAnalogDVCC
S35OAnalogDVCC
69P7.2I/OLVCMOSDVCCOFF
UCA2CLKI/OLVCMOSDVCC
TB0.0I/OLVCMOSDVCC
COM6OAnalogDVCC
S34OAnalogDVCC
70P7.3I/OLVCMOSDVCCOFF
UCA2STEI/OLVCMOSDVCC
TB0.1I/OLVCMOSDVCC
COM7OAnalogDVCC
S33OAnalogDVCC
71P6.1I/OLVCMOSDVCCOFF
R03I/OAnalogDVCC
72P6.2I/OLVCMOSDVCCOFF
R13I/OAnalogDVCC
LCDREFIAnalog-
73P6.3I/OLVCMOSDVCCOFF
R23I/OAnalogDVCC
74R33I/OAnalogDVCC-
LCDCAPI/OAnalogDVCC
75DVSS3PPowerN/A
76DVCC3PPowerN/A
77P7.4I/OLVCMOSDVCCOFF
TA0.1I/OLVCMOSDVCC
78P7.5I/OLVCMOSDVCCOFF
TA1.1I/OLVCMOSDVCC
79P8.0I/OLVCMOSDVCCOFF
UCA3STEI/OLVCMOSDVCC
TB0.2I/OLVCMOSDVCC
DMAE0ILVCMOSDVCC
80P8.1I/OLVCMOSDVCCOFF
UCA3CLKI/OLVCMOSDVCC
TB0.3I/OLVCMOSDVCC
TB0OUTHILVCMOSDVCC
81P8.2I/OLVCMOSDVCCOFF
UCA3RXDOLVCMOSDVCC
UCA3SOMII/OLVCMOSDVCC
MCLKOLVCMOSDVCC
82P8.3I/OLVCMOSDVCCOFF
UCA3TXDOLVCMOSDVCC
UCA3SIMOI/OLVCMOSDVCC
RTCCLKOLVCMOSDVCC
83P7.6I/OLVCMOSDVCCOFF
TA4.1I/OLVCMOSDVCC
DMAE0ILVCMOSDVCC
COUTOLVCMOSDVCC
84P7.7I/OLVCMOSDVCCOFF
TA0.2I/OLVCMOSDVCC
TB0OUTHILVCMOSDVCC
COUTOLVCMOSDVCC
85CH1_INIAnalogPVCC
86CH1_OUTOAnalogPVCC
87PVSSPPowerN/A
88PVCCPPowerN/A
89PVSSPPowerN/A
90CH0_OUTOAnalogPVCC
91CH0_INIAnalogPVCC
92P8.4I/OLVCMOSDVCCOFF
UCB1CLKI/OLVCMOSDVCC
TA1.2I/OLVCMOSDVCC
A10IAnalogDVCC
93P8.5I/OLVCMOSDVCCOFF
UCB1SIMOI/OLVCMOSDVCC
UCB1SDAI/OLVCMOSDVCC
A11IAnalogDVCC
94P8.6I/OLVCMOSDVCCOFF
UCB1SOMII/OLVCMOSDVCC
UCB1SCLI/OLVCMOSDVCC
A12IAnalogDVCC
95P8.7I/OLVCMOSDVCCOFF
UCB1STEI/OLVCMOSDVCC
USSXT_BOUTI/OLVCMOSDVCC
A13IAnalogDVCC
96AVSS5PPowerN/A
97USSXTIN(6)IAnalog1.5 V
98USSXTOUT(6)OAnalog1.5 V
99AVSS1PPowerN/A
100AVCC1PPowerN/A
The signal that is listed first for each pin is the reset default pin name.
Signal Types: I = Input, O = Output, I/O = Input or Output.
Buffer Types: LVCMOS, Analog, or Power (see Table 7-3 for details)
To determine the pin mux encodings for each pin, see Section 9.14.
The power source shown in this table is the I/O power source, which may differ from the module power source.
Do not connect USSXTIN and USSXTOUT pins to AVCC nor to DVCC. USSXTIN does not support bypass mode, so do not drive an external clock on the USSXTIN pin.
Reset States:
OFF = High impedance with Schmitt-trigger input and pullup or pulldown (if available) disabled
PU = Pullup is enabled
PD = Pulldown is enabled
N/A = Not applicable