SLASF12D February   2023  – October 2025 MSPM0G3105 , MSPM0G3106 , MSPM0G3107

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Ramp
      1. 7.6.1 POR and BOR
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
        1. 7.9.1.1 SYSOSC Typical Frequency Accuracy
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
      3. 7.9.3 System Phase Lock Loop (SYSPLL)
      4. 7.9.4 Low Frequency Crystal/Clock
      5. 7.9.5 High Frequency Crystal/Clock
    10. 7.10 Digital IO
      1. 7.10.1 Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 Analog Mux VBOOST
    12. 7.12 ADC
      1. 7.12.1 Electrical Characteristics
      2. 7.12.2 Switching Characteristics
      3. 7.12.3 Linearity Parameters
    13. 7.13 Typical Connection Diagram
    14. 7.14 Temperature Sensor
    15. 7.15 VREF
      1. 7.15.1 Voltage Characteristics
      2. 7.15.2 Electrical Characteristics
    16. 7.16 GPAMP
      1. 7.16.1 Electrical Characteristics
      2. 7.16.2 Switching Characteristics
    17. 7.17 I2C
      1. 7.17.1 I2C Timing Diagram
      2. 7.17.2 I2C Characteristics
      3. 7.17.3 I2C Filter
    18. 7.18 SPI
      1. 7.18.1 SPI
      2. 7.18.2 SPI Timing Diagram
    19. 7.19 UART
    20. 7.20 TIMx
    21. 7.21 TRNG
      1. 7.21.1 TRNG Electrical Characteristics
      2. 7.21.2 TRNG Switching Characteristics
    22. 7.22 Emulation and Debug
      1. 7.22.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  CPU
    2. 8.2  Operating Modes
      1. 8.2.1 Functionality by Operating Mode (MSPM0G310x)
    3. 8.3  Power Management Unit (PMU)
    4. 8.4  Clock Module (CKM)
    5. 8.5  DMA
    6. 8.6  Events
    7. 8.7  Memory
      1. 8.7.1 Memory Organization
      2. 8.7.2 Peripheral File Map
      3. 8.7.3 Peripheral Interrupt Vector
    8. 8.8  Flash Memory
    9. 8.9  SRAM
    10. 8.10 GPIO
    11. 8.11 IOMUX
    12. 8.12 ADC
    13. 8.13 Temperature Sensor
    14. 8.14 VREF
    15. 8.15 GPAMP
    16. 8.16 TRNG
    17. 8.17 AES
    18. 8.18 CRC
    19. 8.19 UART
    20. 8.20 I2C
    21. 8.21 SPI
    22. 8.22 CAN-FD
    23. 8.23 WWDT
    24. 8.24 RTC
    25. 8.25 Timers (TIMx)
    26. 8.26 Device Analog Connections
    27. 8.27 Input/Output Diagrams
    28. 8.28 Serial Wire Debug Interface
    29. 8.29 Bootstrap Loader (BSL)
    30. 8.30 Device Factory Constants
    31. 8.31 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3 Signal Descriptions

Many MSPM0 signals are made available on multiple device pins. The following list describes the column headers:

  1. SIGNAL NAME: The name of the signal which can be connected to one of the specified pins.
  2. PIN TYPE: The signal direction and signal type:
    • I = Input
    • O = Output
    • IO = Input, output, or simultaneous input and output
    • ID = Input with open-drain behavior
    • OD = Output with open-drain behavior
    • IOD = Input, output, or simultaneous input and output with open-drain behavior
    • A = Analog
    • PWR = Power function
  3. DESCRIPTION: A description of the signal.
  4. PIN: Associated pin number.

For additional information on the pin multiplexing scheme, refer to the IOMUX chapter of the MSPM0 G-Series 80MHz Microcontrollers Technical Reference Manual.

Note: The IOMUX only supports connecting one IOMUX-managed digital function to the pin at the same time. However, non-IOMUX managed signals (such as analog inputs and WAKE inputs) can be enabled on a pin at the same time that an IOMUX managed digital function is enabled on the pin. In this case, the designer must verify that no contention exists between the functions enabled on each pin.
Table 6-3 Signal Descriptions
FUNCTION SIGNAL NAME PIN NO. (1) PIN TYPE (2) DESCRIPTION
32 RHB 28 DGS28 20 DGS20
ADC A0_0 31 2 2 I ADC0 analog input 0
A0_1 30 1 1 I ADC0 analog input 1
A0_2 29 28 – I ADC0 analog input 2
A0_3 28 27 20 I ADC0 analog input 3
A0_4 – – – I ADC0 analog input 4
A0_5 – – – I ADC0 analog input 5
A0_6 – – – I ADC0 analog input 6
A0_7 26 25 18 I ADC0 analog input 7
A0_12 18 17 – I ADC0 analog input 12
A1_0 19 18 – I ADC1 analog input 0
A1_1 20 19 – I ADC1 analog input 1
A1_2 21 20 14 I ADC1 analog input 2
A1_3 22 21 15 I ADC1 analog input 3
A1_4 – – – I ADC1 analog input 4
A1_5 – – – I ADC1 analog input 5
A1_6 – – – I ADC1 analog input 6
A1_7 25 24 – I ADC1 analog input 7
BSL BSL_invoke 22 21 15 I Input pin used to invoke bootloader
BSL (I2C) BSLSCL 2 5 – I/O Default I2C BSL clock
BSLSDA 1 4 – I/O Default I2C BSL data
BSL (UART) BSLRX 15 16 12 I Default UART BSL receive
BSLTX 14 15 11 O Default UART BSL transmit
CAN CAN_TX 16
30		 1 1
13		 O CAN-FD transmit data
CAN_RX 17
31		 2 2 I CAN-FD receive data
Clock CLK_OUT 11
13
14
18
26		 14
15
17
25		 10
11
18		 O Configurable clock output
HFCLK_IN 10 13 9 I Digital high-frequency clock input
HFXIN 9 12 8 I Input for high-frequency crystal oscillator HFXT
HFXOUT 10 13 9 O Output for high-frequency crystal oscillator HFXT
LFCLK_IN 8 11 – I Digital low-frequency clock input
LFXIN 7 10 – I Input for low-frequency crystal oscillator LFXT
LFXOUT 8 11 – O Output of low-frequency crystal oscillator LFXT
ROSC 6 9 7 I External resistor used for improving oscillator accuracy
Debug SWCLK 24 23 17 I Serial wire debug input clock
SWDIO 23 22 16 I/O Serial wire debug data input/output
FCC FCC_IN 1
9
16
20		 4
12
19		 8
13		 I Frequency clock counter input
General-Purpose Amplifier GPAMP_IN+ 30 1 1 I GPAMP noninverting terminal input
GPAMP_IN- 22 21 15 I GPAMP inverting terminal input
GPAMP_OUT 26 25 18 O GPAMP output
GPIO PA0 1 4 – I/O General-purpose digital I/O with wake up from SHUTDOWN
PA1 2 5 – I/O General-purpose digital I/O with wake up from SHUTDOWN
PA2 6 9 7 I/O General-purpose digital I/O
PA3 7 10 – I/O General-purpose digital I/O
PA4 8 11 – I/O General-purpose digital I/O
PA5 9 12 8 I/O General-purpose digital I/O
PA6 10 13 9 I/O General-purpose digital I/O
PA7 11 – – I/O General-purpose digital I/O
PA8 12 – – I/O General-purpose digital I/O
PA9 13 14 10 I/O General-purpose digital I/O
PA10 14 15 11 I/O General-purpose digital I/O with wake up from SHUTDOWN
PA11 15 16 12 I/O General-purpose digital I/O with wake up from SHUTDOWN
PA12 16 – 13 I/O General-purpose digital I/O
PA13 17 – – I/O General-purpose digital I/O
PA14 18 17 – I/O General-purpose digital I/O
PA15 19 18 – I/O General-purpose digital I/O
PA16 20 19 – I/O General-purpose digital I/O
PA17 21 20 14 I/O General-purpose digital I/O with wake up from SHUTDOWN
PA18 22 21 15 I/O General-purpose digital I/O with wake up from SHUTDOWN
PA19 23 22 16 I/O General-purpose digital I/O
PA20 24 23 17 I/O General-purpose digital I/O
PA21 25 24 – I/O General-purpose digital I/O
PA22 26 25 18 I/O General-purpose digital I/O
PA23 27 26 19 I/O General-purpose digital I/O
PA24 28 27 20 I/O General-purpose digital I/O
PA25 29 28 – I/O General-purpose digital I/O
PA26 30 1 1 I/O General-purpose digital I/O
PA27 31 2 2 I/O General-purpose digital I/O
PA28 – – – I/O General-purpose digital I/O with wake up from SHUTDOWN
PA29 – – – I/O General-purpose digital I/O
PA30 – – – I/O General-purpose digital I/O
PA31 – – – I/O General-purpose digital I/O with wake up from SHUTDOWN
GPIO PB0 – – – I/O General-purpose digital I/O
PB1 – – – I/O General-purpose digital I/O
PB2 – – – I/O General-purpose digital I/O
PB3 – – – I/O General-purpose digital I/O
PB4 – – – I/O General-purpose digital I/O
PB5 – – – I/O General-purpose digital I/O
PB6 – – – I/O General-purpose digital I/O
PB7 – – – I/O General-purpose digital I/O
PB8 – – – I/O General-purpose digital I/O
PB9 – – – I/O General-purpose digital I/O
PB10 – – – I/O General-purpose digital I/O
PB11 – – – I/O General-purpose digital I/O
PB12 – – – I/O General-purpose digital I/O
PB13 – – – I/O General-purpose digital I/O
PB14 – – – I/O General-purpose digital I/O
PB15 – – – I/O General-purpose digital I/O
PB16 – – – I/O General-purpose digital I/O
PB17 – – – I/O General-purpose digital I/O
PB18 – – – I/O General-purpose digital I/O
PB19 – – – I/O General-purpose digital I/O
PB20 – – – I/O General-purpose digital I/O
PB21 – – – I/O General-purpose digital I/O
PB22 – – – I/O General-purpose digital I/O
PB23 – – – I/O General-purpose digital I/O
PB24 – – – I/O General-purpose digital I/O
PB25 – – – I/O General-purpose digital I/O
PB26 – – – I/O General-purpose digital I/O
PB27 – – – I/O General-purpose digital I/O
I2C I2C0_SCL 2
15		 5
16		 12 I/O I2C0 serial clock
I2C0_SDA 1
14		 4
15		 11 I/O I2C0 serial data
I2C1_SCL 8
15
19
21		 11
16
18
20		 12
14		 I/O I2C1 serial clock
I2C1_SDA 7
14
20
22		 10
15
19
21		 11
15		 I/O I2C1 serial data
Power VSS 5 8 6 P Ground supply
VDD 4 7 5 P Power supply
VCORE 32 3 3 P Regulated core power supply output
QFN Pad Pad – – P QFN package exposed thermal pad. TI recommends connection to VSS.
RTC RTC_OUT 13
31		 2
14		 2
10		 O RTC clock output
SPI SPI0_CS0 6
12		 9 7 I/O SPI0 chip-select 0
SPI0_CS1 7 10 – I/O SPI0 chip-select 1
SPI0_CS2 28 27 20 I/O SPI0 chip-select 2
SPI0_CS3 27 26 19 I/O SPI0 chip-select 3
SPI0_SCK 10
15
16		 13
16		 9
12
13		 I/O SPI0 clock signal input – SPI peripheral mode
Clock signal output – SPI controller mode
SPI0_POCI 8
14
17		 11
15		 11 I/O SPI0 controller in/peripheral out
SPI0_PICO 9
13
18		 12
14
17		 8
10		 I/O SPI0 controller out/peripheral in
SPI1_CS0 6
30		 1
9		 1
7		 I/O SPI1 chip-select 0
SPI1_CS1 31 2 2 I/O SPI1 chip-select 1
SPI1_CS2 19 18 – I/O SPI1 chip-select 2
SPI1_CS3 29 28 – I/O SPI1 chip-select 3
SPI1_SCK 21 20 14 I/O SPI1 clock signal input – SPI peripheral mode
Clock signal output – SPI controller mode
SPI1_POCI 20 19 – I/O SPI1 controller in/peripheral out
SPI1_PICO 22 21 15 I/O SPI1 controller out/peripheral in
System NRST 3 6 4 I Reset input active low
Timer TIMG0_C0 9
16
27		 12
26		 8
13
19		 I/O General purpose timer 0 CCR0 capture input/ compare output
TIMG0_C1 10
17
28		 13
27		 9
20		 I/O General purpose timer 0 CCR1 capture input/ compare output
TIMG6_C0 9
25		 12
24		 8 I/O General purpose timer 6 CCR0 capture input/ compare output
TIMG6_C1 10
26		 13
25		 9
18		 I/O General purpose timer 6 CCR1 capture input/ compare output
TIMG7_C0 7
21
27
30		 1
10
20
26		 1
14
19		 I/O General purpose timer 7 CCR1 capture input/ compare output
TIMG7_C1 6
8
11
22
28
31		 2
9
11
21
27 		2
7
15
20 		I/O General purpose timer 7 CCR1 capture input/ compare output
TIMG8_C0 2
7
9
11
25
27
30		 1
5
10
12
24
26		 1
8
19		 I/O General purpose timer 8 CCR0 capture input/ compare output
Timer (continued) TIMG8_C1 1
6
8
10
26
31		 2
4
9
11
13
25		 2
7
9
18 		I/O General purpose timer 8 CCR1 capture input/ compare output
TIMG8_IDX 2
11
19		 5
18		 – I General purpose timer 8 quadrature encoder index pulse input
TIMG12_C0 14
18		 15
17		 11 I/O 32-bit general purpose timer 0 CCR0 capture input/ compare output
TIMG12_C1 29 28 – I/O 32-bit general purpose timer 0 CCR1 capture input/ compare output
TIMA0_C0 1
12
25		 4
24		 – I/O Advanced control timer 0 CCR0 capture input/compare output
TIMA0_C0N 13
26		 14
25		 10
18		 I/O Advanced control timer 0 CCR0 capture input/compare output (inverting)
TIMA0_C1 2
7
11
13
26		 5
10
14
25		 10
18		 I/O Advanced control timer 0 CCR1 capture input/ compare output
TIMA0_C1N 8
13
29		 11
14
28		 10 I/O Advanced control timer 0 CCR1 capture input/ compare output (inverting)
Timer (continued) TIMA0_C2 7
11
14
19		 10
15
18		 11 I/O Advanced control timer 0 CCR2 capture input/ compare output
TIMA0_C2N 10
15
20		 13
16
19		 9
12		 I/O Advanced control timer 0 CCR2 capture input/ compare output (inverting)
TIMA0_C3 8
16
21
27
29		 11
20
26
28		 13
14
19		 I/O Advanced control timer 0 CCR3 capture input/ compare output
TIMA0_C3N 17
22
28		 21
27		 15
20		 I/O Advanced control timer 0 CCR3 capture input/ compare output (inverting)
TIMA1_C0 14
19
21		 15
18
20		 11
14		 I/O Advanced control timer 1 CCR0 capture input/ compare output
TIMA1_C0N 12
19		 18 – I/O Advanced control timer 0 CCR3 capture input/ compare output (inverting)
TIMA1_C1 15
20
22
28		 16
19
21
27		 12
15
20		 I/O Advanced control timer 1 CCR1 capture input/ compare output
TIMA1_C1N 13
20		 14
19		 10 I/O Advanced control timer 1 CCR1 capture input/ compare output (inverting)
Timer (continued) TIMA_FAL0 10
30		 1
13		 1
9		 I Advanced control timer 0 fault handling input
TIMA_FAL1 1
9		 4
12		 8 I Advanced control timer 1 fault handling input
TIMA_FAL2 2
31		 2
5		 2 I Advanced control timer 2 fault handling input
UART UART0_TX 1
14		 4
15		 11 O UART0 transmit data
UART0_RX 2
15		 5
16		 12 I UART0 receive data
UART0_CTS 13
18		 14
17		 10 I UART0 "clear to send" flow control input
UART0_RTS 12
19		 18 – O UART0 "request to send" flow control output
UART1_TX 12
21		 20 14 O UART1 transmit data
UART1_RX 13
22		 14
21		 10
15		 I UART1 receive data
UART1_CTS 25 24 – I UART1 "clear to send" flow control input
UART1_RTS 26 25 18 O UART1 "request to send" flow control output
UART2_TX 25
27		 24
26		 19 O UART2 transmit data
UART2_RX 26
28		 25
27		 18
20		 I UART2 receive data
UART2_CTS 7 10 – I UART2 "clear to send" flow control input
UART2_RTS 8 11 – O UART2 "request to send" flow control output
UART UART3_TX 18
30		 1
17		 1 O UART3 transmit data
UART3_RX 17
29		 28 – I UART3 receive data
UART3_CTS 16
27		 26 13
19		 I UART3 "clear to send" flow control input
UART3_RTS 17
28		 27 20 O UART3 "request to send" flow control output
Voltage Reference (3) VREF+ 27 26 19 I/O Voltage reference (VREF) power supply - external reference input / internal reference output
VREF- 25 24 – I/O Voltage reference (VREF) ground supply - external reference input / internal reference output
(1) – = not available
(2) I = input, O = output, I/O = input or output, P = power
(3) When using VREF± to bring in an external voltage reference for analog peripherals such as the ADC, a decoupling capacitor must be placed on VREF+ to VREF-/GND with a capacitance based on the external reference source