SLASF12D February   2023  – October 2025 MSPM0G3105 , MSPM0G3106 , MSPM0G3107

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Ramp
      1. 7.6.1 POR and BOR
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
        1. 7.9.1.1 SYSOSC Typical Frequency Accuracy
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
      3. 7.9.3 System Phase Lock Loop (SYSPLL)
      4. 7.9.4 Low Frequency Crystal/Clock
      5. 7.9.5 High Frequency Crystal/Clock
    10. 7.10 Digital IO
      1. 7.10.1 Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 Analog Mux VBOOST
    12. 7.12 ADC
      1. 7.12.1 Electrical Characteristics
      2. 7.12.2 Switching Characteristics
      3. 7.12.3 Linearity Parameters
    13. 7.13 Typical Connection Diagram
    14. 7.14 Temperature Sensor
    15. 7.15 VREF
      1. 7.15.1 Voltage Characteristics
      2. 7.15.2 Electrical Characteristics
    16. 7.16 GPAMP
      1. 7.16.1 Electrical Characteristics
      2. 7.16.2 Switching Characteristics
    17. 7.17 I2C
      1. 7.17.1 I2C Timing Diagram
      2. 7.17.2 I2C Characteristics
      3. 7.17.3 I2C Filter
    18. 7.18 SPI
      1. 7.18.1 SPI
      2. 7.18.2 SPI Timing Diagram
    19. 7.19 UART
    20. 7.20 TIMx
    21. 7.21 TRNG
      1. 7.21.1 TRNG Electrical Characteristics
      2. 7.21.2 TRNG Switching Characteristics
    22. 7.22 Emulation and Debug
      1. 7.22.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  CPU
    2. 8.2  Operating Modes
      1. 8.2.1 Functionality by Operating Mode (MSPM0G310x)
    3. 8.3  Power Management Unit (PMU)
    4. 8.4  Clock Module (CKM)
    5. 8.5  DMA
    6. 8.6  Events
    7. 8.7  Memory
      1. 8.7.1 Memory Organization
      2. 8.7.2 Peripheral File Map
      3. 8.7.3 Peripheral Interrupt Vector
    8. 8.8  Flash Memory
    9. 8.9  SRAM
    10. 8.10 GPIO
    11. 8.11 IOMUX
    12. 8.12 ADC
    13. 8.13 Temperature Sensor
    14. 8.14 VREF
    15. 8.15 GPAMP
    16. 8.16 TRNG
    17. 8.17 AES
    18. 8.18 CRC
    19. 8.19 UART
    20. 8.20 I2C
    21. 8.21 SPI
    22. 8.22 CAN-FD
    23. 8.23 WWDT
    24. 8.24 RTC
    25. 8.25 Timers (TIMx)
    26. 8.26 Device Analog Connections
    27. 8.27 Input/Output Diagrams
    28. 8.28 Serial Wire Debug Interface
    29. 8.29 Bootstrap Loader (BSL)
    30. 8.30 Device Factory Constants
    31. 8.31 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.12.1 Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted), all TYP values are measured at 25℃ and all accuracy parameters are measured using 12-bit resolution mode (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Vin(ADC) Analog input voltage range(1) Applies to all ADC analog input pins 0 VDD V
VR+ Positive ADC reference voltage VR+ sourced from VDD VDD V
VR+ sourced from external reference pin (VREF+) 1.4 VDD V
VR+ sourced from internal reference (VREF) VREF V
VR- Negative ADC reference voltage 0 V
FS ADC sampling frequency  RES = 0x0 (12-bit mode) 4 Msps
RES = 0x1 (10-bit mode) 4
RES = 0x2 (8-bit mode) , SCOMP = 2 5.3
I(ADC) Operating supply current
into VDD terminal 		 FS = 4MSPS, VR+ = VDD 1.75(2) mA
CS/H ADC sample-and-hold capacitance 3.3 pF
Rin ADC input resistance 0.5 kΩ
ENOB Effective number of bits f_in = 10KHz, External reference (3) 10.9 11.1 bit
f_in = 10KHz, External reference (3), HW Averaging Enabled, 16 Samples and 2bit shift 12.3 12.5
f_in = 10KHz, Internal reference, VR+ = VREF = 2.5V (VRSEL = 1h)(5) 9.9 10.8
f_in = 10KHz, Internal reference, VR+ = VREF = 2.5V (VRSEL = 2h) 9.2
SNR Signal-to-noise ratio f_in = 10KHz, External reference (3) 68 dB
f_in = 10KHz, External reference (3), HW Averaging Enabled, 16 Samples and 2bit shift 78
f_in = 10KHz, Internal reference, VR+ = VREF = 2.5V (VRSEL = 1h)(5) 66
f_in = 10KHz, Internal reference, VR+ = VREF = 2.5V (VRSEL = 2h) 57
PSRRDC Power supply rejection ratio, DC External reference (3), VDD = VDD(min) to VDD(max) 62 dB
VDD = VDD(min) to VDD(max)
Internal reference, VR+ = VREF = 2.5V 		 53
PSRRAC Power supply rejection ratio, AC External reference (3), ΔVDD = 0.1 V at 1 kHz 61 dB
ΔVDD = 0.1 V at 1 kHz
Internal reference, VR+ = VREF = 2.5V 		 52
Twakeup ADC Wakeup Time Assumes internal reference is active 5 us
VSupplyMon Supply Monitor voltage divider (VDD/3) accuracy ADC input channel: Supply Monitor(4)(6) -1.5 1.5  %
ISupplyMon Supply Monitor voltage divider current consumption ADC input channel: Supply Monitor 10 uA
(1) The analog input voltage range must be within the selected ADC reference voltage range VR+ to VR– for valid conversion results.
(2) The internal reference (VREF) supply current is not included in current consumption parameter I(ADC).
(3) All external reference specifications are measured with VR+ = VREF+ = VDD = 3.3V and VR- = VREF- = VSS = 0V and external 1uF cap on VREF+ pin
(4) Analog power supply monitor. Analog input on channel 15 is disconnected and is internally connected to the voltage divider which is VDD/3.
(5) Please note that to achieve this ENOB using internal reference VREF, VRSEL bit in MEMCTL register needs to be set to the external reference mode. This will set the REFN as VREF- and REFP as VREF+. In this configuration ,no external connections can be made on the VREF- and VREF+ pins. The REFN pin should be connected to device ground.
(6) Characterized using external reference  (VREFSEL = 1)