SLASF86C October   2023  – September 2025 MSPM0G3105-Q1 , MSPM0G3106-Q1 , MSPM0G3107-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Ramp
      1. 7.6.1 POR and BOR
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
        1. 7.9.1.1 SYSOSC Typical Frequency Accuracy
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
      3. 7.9.3 System Phase Lock Loop (SYSPLL)
      4. 7.9.4 Low Frequency Crystal/Clock
      5. 7.9.5 High Frequency Crystal/Clock
    10. 7.10 Digital IO
      1. 7.10.1 Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 Analog Mux VBOOST
    12. 7.12 ADC
      1. 7.12.1 Electrical Characteristics
      2. 7.12.2 Switching Characteristics
      3. 7.12.3 Linearity Parameters
    13. 7.13 Typical Connection Diagram
    14. 7.14 Temperature Sensor
    15. 7.15 VREF
      1. 7.15.1 Voltage Characteristics
      2. 7.15.2 Electrical Characteristics
    16. 7.16 GPAMP
      1. 7.16.1 Electrical Characteristics
      2. 7.16.2 Switching Characteristics
    17. 7.17 I2C
      1. 7.17.1 I2C Timing Diagram
      2. 7.17.2 I2C Characteristics
      3. 7.17.3 I2C Filter
    18. 7.18 SPI
      1. 7.18.1 SPI
      2. 7.18.2 SPI Timing Diagram
    19. 7.19 UART
    20. 7.20 TIMx
    21. 7.21 TRNG
      1. 7.21.1 TRNG Electrical Characteristics
      2. 7.21.2 TRNG Switching Characteristics
    22. 7.22 Emulation and Debug
      1. 7.22.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  CPU
    2. 8.2  Operating Modes
      1. 8.2.1 Functionality by Operating Mode (MSPM0G310x)
    3. 8.3  Power Management Unit (PMU)
    4. 8.4  Clock Module (CKM)
    5. 8.5  DMA
    6. 8.6  Events
    7. 8.7  Memory
      1. 8.7.1 Memory Organization
      2. 8.7.2 Peripheral File Map
      3. 8.7.3 Peripheral Interrupt Vector
    8. 8.8  Flash Memory
    9. 8.9  SRAM
    10. 8.10 GPIO
    11. 8.11 IOMUX
    12. 8.12 ADC
    13. 8.13 Temperature Sensor
    14. 8.14 VREF
    15. 8.15 GPAMP
    16. 8.16 TRNG
    17. 8.17 AES
    18. 8.18 CRC
    19. 8.19 UART
    20. 8.20 I2C
    21. 8.21 SPI
    22. 8.22 CAN-FD
    23. 8.23 WWDT
    24. 8.24 RTC
    25. 8.25 Timers (TIMx)
    26. 8.26 Device Analog Connections
    27. 8.27 Input/Output Diagrams
    28. 8.28 Serial Wire Debug Interface
    29. 8.29 Bootstrap Loader (BSL)
    30. 8.30 Device Factory Constants
    31. 8.31 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DGS|28
  • PM|64
  • RGZ|48
  • RHB|32
  • DGS|32
  • PT|48
  • DGS|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Revision History

Changes from May 31, 2024 to September 30, 2025 (from Revision (May 2024) to Revision (September 2025))

  • Added pitch and package identifier details to package options listGo
  • Added comlementary output to the advanced timer feature descriptionGo
  • Added WWDT acronym to the windowed watch dog timer feature descriptionGo
  • Changed communications feature section formatting for clarityGo
  • Added "open drain" to 5V IO descriptionGo
  • Added number of high speed IOs to Flexible I/O Features sectionGo
  • Updated Optimized Low-Power Mode sectionGo
  • Updated functional safety branding to indicate ASIL B complianceGo
  • Updated Features page to match supply current characteristics electrical specifications Go
  • Added "R" to OPNs to designate distribution formatGo
  • Moved Digital Features by IO Type table to beginning of Pin Attributes sectionGo
  • Added pin type information to the beginning of the Signal Description sectionGo
  • Added footnote to absolute maximum ratings section for diode current injection limitation on PA21 GPIO pinGo
  • Added I_VDD/I_VSS missing footnote to absolute maximum ratings for lower current at VDD=1.62VGo
  • Updated LFOSC start-up time specification from 1.7ms to 1ms Go
  • Updated Digital IO VOL specification for HSIO to correctly reference temperature condition to match with other IO types for this specGo
  • Updated Digital IO Electrical specifications and Switching specifications sections with added footnote for series current limiting resistor when using HDIO in DRV=1 drive strength settingGo
  • Added Digital IO switching specifications line item for port output frequency for HDIO operation with DRV=1 drive strength settingGo
  • Added condition for comparator electrical specifications section on I_comp specification HCYCLE register settingGo
  • Updated power-on reset voltage level specificationsGo
  • Updated BOR COLD specification sectionGo
  • Changed the VBOR0- falling from 1.56 to 1.55Go
  • Added SLEEP0 wakeup timeGo
  • Changed "fSYSOSC additional undershoot accuracy during tsettle" min from -11 to -16Go
  • Changed SYSPLLCLK0/1from 1MHz to 2.5MHzGo
  • Changed SYSPLL RMS cycle-to-cycle jitter from 24ps to 60psGo
  • Changed the SYSPLL typical start up time from 14us to 7us, and the maximum start up time from 24us to 18usGo
  • Changed VDD ≥ 2.7V, DRV = 1, CL= 20pF specification from 40MHz to 32MHzGo
  • 32Changed VDD ≥ 2.7V, DRV = 1, CL= 20pF specification from 40MHz to 32MHzGo
  • Changed I_VBST from 0.7uA to 0.8uAGo
  • Added "f_in = 10KHz" test conditionGo
  • Changed V_SupplyMon max from 1% to 1.5%Go
  • Changed offset error from +/-2mV to +/-3.5mVGo
  • Changed gain error from +/-3LSB to +/-4LSBGo
  • Changed temperature sensor settling time from 10us to 12.5usGo
  • Removed +/- from output load current and only made it +4mA.Go
  • Added temperature senor and VREF to Operating Conditions tableGo
  • Updated table with accurate detailsGo
  • Changed the temperature sensor calibration condition from 1.4V to 3.3V with the correct register configuration settingGo
  • Added PART and VARIANT to USERID table for YCJ packagesGo