SLASF59A May   2023  – December 2023 MSPM0L1304-Q1 , MSPM0L1305-Q1 , MSPM0L1306-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 POR and BOR
      2. 7.6.2 Power Supply Ramp
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
    10. 7.10 Digital IO
      1. 7.10.1 Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 Analog Mux VBOOST
    12. 7.12 ADC
      1. 7.12.1 Electrical Characteristics
      2. 7.12.2 Switching Characteristics
      3. 7.12.3 Linearity Parameters
      4. 7.12.4 Typical Connection Diagram
    13. 7.13 Temperature Sensor
    14. 7.14 VREF
      1. 7.14.1 Voltage Characteristics
      2. 7.14.2 Electrical Characteristics
    15. 7.15 COMP
      1. 7.15.1 Comparator Electrical Characteristics
    16. 7.16 GPAMP
      1. 7.16.1 Electrical Characteristics
      2. 7.16.2 Switching Characteristics
    17. 7.17 OPA
      1. 7.17.1 Electrical Characteristics
      2. 7.17.2 Switching Characteristics
      3. 7.17.3 PGA Mode
    18. 7.18 I2C
      1. 7.18.1 I2C Characteristics
      2. 7.18.2 I2C Filter
      3. 7.18.3 I2C Timing Diagram
    19. 7.19 SPI
      1. 7.19.1 SPI
      2. 7.19.2 SPI Timing Diagram
    20. 7.20 UART
    21. 7.21 TIMx
    22. 7.22 Emulation and Debug
      1. 7.22.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  CPU
    2. 8.2  Operating Modes
      1. 8.2.1 Functionality by Operating Mode
    3. 8.3  Power Management Unit (PMU)
    4. 8.4  Clock Module (CKM)
    5. 8.5  DMA
    6. 8.6  Events
    7. 8.7  Memory
      1. 8.7.1 Memory Organization
      2. 8.7.2 Peripheral File Map
      3. 8.7.3 Peripheral Interrupt Vector
    8. 8.8  Flash Memory
    9. 8.9  SRAM
    10. 8.10 GPIO
    11. 8.11 IOMUX
    12. 8.12 ADC
    13. 8.13 Temperature Sensor
    14. 8.14 VREF
    15. 8.15 COMP
    16. 8.16 CRC
    17. 8.17 GPAMP
    18. 8.18 OPA
    19. 8.19 I2C
    20. 8.20 SPI
    21. 8.21 UART
    22. 8.22 WWDT
    23. 8.23 Timers (TIMx)
    24. 8.24 Device Analog Connections
    25. 8.25 Input/Output Diagrams
    26. 8.26 Serial Wire Debug Interface
    27. 8.27 Bootstrap Loader (BSL)
    28. 8.28 Device Factory Constants
    29. 8.29 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DGS|28
  • DYY|16
  • RGE|24
  • RHB|32
  • DGS|32
  • DGS|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.10.1 Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH High level input voltage ODIO (1) VDD ≥ 1.62V 0.7×VDD 5.5 V
VDD ≥ 2.7V 2 5.5 V
All I/O except ODIO & Reset VDD ≥ 1.62V 0.7×VDD VDD+0.3 V
VIL Low level input voltage ODIO VDD ≥ 1.62V -0.3 0.3×VDD V
VDD ≥ 2.7V -0.3 0.8 V
All I/O except ODIO & Reset VDD ≥ 1.62V -0.3 0.3×VDD V
VHYS Hysteresis ODIO 0.05×VDD V
All I/O except ODIO 0.1×VDD V
Ilkg High-Z leakage current SDIO(2)(3) ±50(4) nA
RPU Pull up resistance All I/O except ODIO 40 kΩ
RPD Pull down resistance 40 kΩ
CI Input capacitance 5 pF
VOH High level output voltage SDIO VDD ≥ 2.7V, |IIO|,max = 6mA
VDD ≥ 1.71V, |IIO|,max = 2mA
VDD ≥ 1.62V, |IIO|,max = 1.5mA
-40 °C ≤Tj≤25 °C		 VDD-0.4 V
VDD ≥ 2.7V, |IIO|,max = 6mA
VDD ≥ 1.71V, |IIO|,max = 2mA
VDD ≥ 1.62V, |IIO|,max = 1.5mA
-40 °C ≤Tj≤130 °C		 VDD-0.45
HSIO VDD ≥ 2.7V, DRV = 1, |IIO|,max = 6mA
VDD ≥ 1.71V, DRV = 1, |IIO|,max = 3mA
VDD ≥ 1.62V, DRV = 1, |IIO|,max = 2mA
-40 °C ≤Tj≤25 °C		 VDD-0.4
VDD ≥ 2.7V, DRV = 1, |IIO|,max = 6mA
VDD ≥ 1.71V, DRV = 1, |IIO|,max = 3mA
VDD ≥ 1.62V, DRV = 1, |IIO|,max = 2mA
-40 °C ≤Tj≤130 °C		 VDD-0.4
VDD ≥ 2.7V, DRV = 0, |IIO|,max = 4mA
VDD ≥ 1.71V, DRV = 0, |IIO|,max = 2mA
VDD ≥ 1.62V, DRV = 0, |IIO|,max = 1.5mA
-40 °C ≤Tj≤25 °C		 VDD-0.45
VDD ≥ 2.7V, DRV = 0, |IIO|,max = 4mA
VDD ≥ 1.71V, DRV = 0, |IIO|,max = 2mA
VDD ≥ 1.62V, |IIO|,max = 1.5mA
-40 °C ≤Tj≤130 °C		 VDD-0.45
VOL Low level output voltage SDIO VDD ≥ 2.7V, |IIO|,max = 6mA
VDD ≥ 1.71V, |IIO|,max = 2mA
VDD ≥ 1.62V, |IIO|,max = 1.5mA
-40 °C ≤Tj≤25 °C		 0.4 V
VDD ≥ 2.7V, |IIO|,max = 6mA
VDD ≥ 1.71V, |IIO|,max = 2mA
VDD ≥ 1.62V, |IIO|,max = 1.5mA
-40 °C ≤Tj≤130 °C		 0.45
HSIO VDD ≥ 2.7V, DRV = 1, |IIO|,max = 6mA
VDD ≥ 1.71V, DRV = 1, |IIO|,max = 3mA
VDD ≥ 1.62V, DRV = 1, |IIO|,max = 2mA
Tj≤85 °C		 0.4
VDD ≥ 2.7V, DRV = 1, |IIO|,max = 6mA
VDD ≥ 1.71V, DRV = 1, |IIO|,max = 3mA
VDD ≥ 1.62V, DRV = 1, |IIO|,max = 2mA
-40 °C ≤Tj≤130 °C		 0.45
VDD ≥ 2.7V, DRV = 0, |IIO|,max = 4mA
VDD ≥ 1.71V, DRV = 0, |IIO|,max = 2mA
VDD ≥ 1.62V, DRV = 0, |IIO|,max = 1.5mA
Tj≤85 °C		 0.4
VDD ≥ 2.7V, DRV = 0, |IIO|,max = 4mA
VDD ≥ 1.71V, DRV = 0, |IIO|,max = 2mA
VDD ≥ 1.62V, DRV = 0, |IIO|,max = 1.5mA
-40 °C ≤Tj≤130 °C		 0.45

ODIO

 VDD ≥ 2.7V, IOL,max = 8mA
VDD ≥ 1.71V, IOL,max = 4mA
-40 °C ≤Tj≤25 °C		 0.4
VDD ≥ 2.7V, IOL,max = 8mA
VDD ≥ 1.71V, IOL,max = 4mA
-40 °C ≤Tj≤130 °C		 0.45
(1) I/O Types: ODIO = 5V Tolerant Open-Drain , SDIO = Standard-Drive , HSIO = High-Speed
(2) The leakage current is measured with VSS or VDD applied to the corresponding pins, unless otherwise noted.
(3) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is disabled.
(4) This value is for SDIO not muxed with any analog inputs. If the SDIO is muxed with analog inputs then the leakage can be as high as 100nA.