SBOS690A July 2016 – December 2019 OPA2626
The circuit illustrated in Figure 61 consists of the SAR ADC driver, a low-pass filter, and the SAR ADC. The SAR ADC driver circuit consists of an OPA2626 configured in an inverting gain of 1. The filter consists of RFLT and CFLT, connected between the OPA2626 output and the ADS8860 input. Selecting the proper values for each of these passive components is critical to obtain the best performance from the ADC. Capacitor CFLT serves as a charge reservoir, providing the necessary charge to the ADC sampling capacitors. The dynamic load presented by the ADC creates a glitch on the filter capacitor, CFLT. To minimize the magnitude of this glitch, choose a value for CFLT large enough to maintain a glitch amplitude of less than 100 mV. Maintaining such a low glitch amplitude at the amplifier output makes sure that the amplifier remains in the linear operating region, and results in a minimum settling time. Using Equation 6, a 10-nF capacitor is selected for CFLT.
Connecting a 10-nF capacitor directly to the OPA2626 output degrades the OPA2626 phase margin and results in stability and settling-time problems. To properly drive the 10-nF capacitor, use a series resistor (RFLT) to isolate the capacitor, CFLT, from the OPA2626. RFLT must be sized based upon several constraints. To determination a suitable value for RFLT, consider the impact upon the THD resulting from the voltage divider effect from RFLT reacting with the switch resistance (RSW) of the ADC input circuit, as well as the impact of the output impedance upon amplifier stability. In this example, 4.7-Ω resistors are selected. In this design example, Figure 13 can be used to estimate a suitable value for RISO. RISO represents the total resistance in series with CFLT, and in this example is equivalent to 2 × RFLT.
|For step-by-step design procedure, circuit schematics, bill of materials, printed circuit board (PCB) files, simulation results, and test results, refer to the Power-optimized 16-bit 1MSPS Data Acquisition Block for Lowest Distortion and Noise Reference Design reference guide.|