SBOS690A July 2016 – December 2019 OPA2626
An ADC input driver circuit consists of two parts: a driving amplifier and a fly-wheel RC filter. The amplifier is used for signal conditioning of the input voltage and the low output impedance provides a buffer between the signal source and the ADC input. The RC filter helps attenuate the sampling charge-injection from the switched-capacitor input stage of the ADC and acts as an antialiasing filter to band-limit the wideband noise contributed by the front-end circuit. The design of the ADC input driver involves optimizing the bandwidth of the circuit, driven by the following requirements:
CFLT is chosen based upon Equation 7. CFLT is chosen to be 1 nF.
Connecting a 1-nF capacitor directly to the output of the OPA2626 degrades the OPA2626 phase margin and results in stability and settling time problems. To properly drive the 1-nF capacitor, a series resistor, RFLT, is used to isolate the capacitor, CFLT, from the OPA2626. RFLT must be sized based upon several constraints. To determination a suitable value for RFLT, the system designer must consider the impact upon the THD resulting from the voltage divider effect from RFLT reacting with the switch resistance, RSW, of the ADC input circuit as well as the impact of the output impedance upon amplifier stability. In this example 12.4-Ω resistors are selected. In this design example, Figure 12 can be used to estimate a suitable value for RISO. RISO represents the total resistance in series with CFLT, which in this example is equivalent to 2 × RFLT.
|For step-by-step design procedure, circuit schematics, bill of materials, printed circuit board (PCB) files, simulation results, and test results, refer to the 18-Bit Data Acquisition (DAQ) Block Optimized for 1-μs Full-Scale Step Response reference guide.|