SBOS969E October   2019  – May 2021 OPA2991 , OPA4991 , OPA991

PRODMIX  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information for Single Channel
    5. 6.5 Thermal Information for Dual Channel
    6. 6.6 Thermal Information for Quad Channel
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Protection Circuitry
      2. 7.3.2  EMI Rejection
      3. 7.3.3  Thermal Protection
      4.     
      5. 7.3.4  Capacitive Load and Stability
      6. 7.3.5  Common-Mode Voltage Range
      7. 7.3.6  Phase Reversal Protection
      8. 7.3.7  Electrical Overstress
      9. 7.3.8  Overload Recovery
      10. 7.3.9  Typical Specifications and Distributions
      11. 7.3.10 Packages With an Exposed Thermal Pad
      12. 7.3.11 Shutdown
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Low-Side Current Measurement
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 TINA-TI (Free Software Download)
        2. 11.1.1.2 TI Precision Designs
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Configuration and Functions

GUID-58A2EDD2-DB57-472A-A3B5-84AE7B42315A-low.svg
DRL package is preview only.
Figure 5-1 OPA991 DBV, T DCK, and DRL Package(A)
5-Pin SOT-23, SC70, and SOT-553
Top View
GUID-C1B96E2B-930C-41B9-9086-3EA7BD6951F2-low.svgFigure 5-2 OPA991 DCK Package
5-Pin SC70
Top View
Table 5-1 Pin Functions: OPA991
PIN I/O DESCRIPTION
NAME DBV, DRL DCK
IN+ 3 1 I Noninverting input
IN– 4 3 I Inverting input
OUT 1 4 O Output
V+ 5 5 Positive (highest) power supply
V– 2 2 Negative (lowest) power supply
GUID-A9260097-D50F-4F19-A56F-0E2DA4034450-low.gif
DRL package is preview only.
Figure 5-3 OPA991S DBV and DRL Package(A)
6-Pin SOT-23 and SOT-563
Top View
Table 5-2 Pin Functions: OPA991S
PIN I/O DESCRIPTION
NAME NO.
+IN 3 I Noninverting input
–IN 4 I Inverting input
OUT 1 O Output
SHDN 5 I Shutdown: low = amplifier enabled, high = amplifier disabled. See Section 7.3.11 for more information.
V+ 6 Positive (highest) power supply
V– 2 Negative (lowest) power supply
GUID-8E9A7C42-C6DA-4C20-BA20-2C6217D23BF8-low.svgFigure 5-4 OPA2991 D, DDF, DGK, and PW Package
8-Pin SOIC, SOT-23-8, TSSOP, and VSSOP
Top View
GUID-F6592023-B378-49A0-B2D0-5B8B0CEA2F49-low.svg
Connect thermal pad to V–. See Section 7.3.10 for more information.
Figure 5-5 OPA2991 DSG Package(A)
8-Pin WSON With Exposed Thermal Pad
Top View
Table 5-3 Pin Functions: OPA2991
PIN I/O DESCRIPTION
NAME NO.
+IN A 3 I Noninverting input, channel A
+IN B 5 I Noninverting input, channel B
–IN A 2 I Inverting input, channel A
–IN B 6 I Inverting input, channel B
OUT A 1 O Output, channel A
OUT B 7 O Output, channel B
V+ 8 Positive (highest) power supply
V– 4 Negative (lowest) power supply
GUID-0F3B7677-912B-4327-9231-1014F52ED81E-low.svg
Package is preview only.
Figure 5-6 OPA2991S DGS Package(A)
10-Pin VSSOP
Top View
GUID-2C1E1E20-92E3-4C62-BC61-BFC1BAD4BC9E-low.svgFigure 5-7 OPA2991S RUG Package
10-Pin X2QFN
Top View
Table 5-4 Pin Functions: OPA2991S
PIN I/O DESCRIPTION
NAME VSSOP X2QFN
+IN A 3 10 I Noninverting input, channel A
+IN B 7 4 I Noninverting input, channel B
–IN A 2 9 I Inverting input, channel A
–IN B 8 5 I Inverting input, channel B
OUT A 1 8 O Output, channel A
OUT B 9 6 O Output, channel B
SHDN1 5 2 I Shutdown, channel 1: low = amplifier enabled, high = amplifier disabled. See Section 7.3.11 for more information.
SHDN2 6 3 I Shutdown, channel 2: low = amplifier enabled, high = amplifier disabled. See Section 7.3.11 for more information.
V+ 10 7 Positive (highest) power supply
V– 4 1 Negative (lowest) power supply
GUID-6FC18D1C-B288-4D42-80AD-7BB063DAE938-low.svgFigure 5-8 OPA4991 D and PW Package
14-Pin SOIC and TSSOP
Top View
GUID-7DF2DD1B-AC70-4314-9E4E-B7B0459F3A7E-low.svgFigure 5-10 OPA4991 RUC Package
14-Pin WQFN With Exposed Thermal Pad
Top View
GUID-3AC63543-385A-42E3-8EB6-C6AD514AF113-low.svg
Connect thermal pad to V–. See Section 7.3.10 for more information.
Package is preview only.
Figure 5-9 OPA4991 RTE Package(A)(B)
16-Pin WQFN With Exposed Thermal Pad
Top View
Table 5-5 Pin Functions: OPA4991
PIN I/O DESCRIPTION
NAME SOIC, TSSOP WQFN
IN1+ 3 1 I Noninverting input, channel 1
IN1– 2 16 I Inverting input, channel 1
IN2+ 5 3 I Noninverting input, channel 2
IN2– 6 4 I Inverting input, channel 2
IN3+ 10 10 I Noninverting input, channel 3
IN3– 9 9 I Inverting input, channel 3
IN4+ 12 12 I Noninverting input, channel 4
IN4– 13 13 I Inverting input, channel 4
NC 6, 7 Do not connect
OUT1 1 15 O Output, channel 1
OUT2 7 5 O Output, channel 2
OUT3 8 8 O Output, channel 3
OUT4 14 14 O Output, channel 4
V+ 4 2 Positive (highest) power supply
V– 11 11 Negative (lowest) power supply
GUID-9F1C8C8F-C3B4-4007-949D-99C889E08AA1-low.svg
Package is preview only.
Figure 5-11 OPA4991S RTE Package(A)
16-Pin WQFN With Exposed Thermal Pad
Top View
Table 5-6 Pin Functions: OPA4991S
PIN I/O DESCRIPTION
NAME NO.
IN1+ 1 I Noninverting input, channel 1
IN1– 16 I Inverting input, channel 1
IN2+ 3 I Noninverting input, channel 2
IN2– 4 I Inverting input, channel 2
IN3+ 10 I Noninverting input, channel 3
IN3– 9 I Inverting input, channel 3
IN4+ 12 I Noninverting input, channel 4
IN4– 13 I Inverting input, channel 4
OUT1 15 O Output, channel 1
OUT2 5 O Output, channel 2
OUT3 8 O Output, channel 3
OUT4 14 O Output, channel 4
SHDN12 6 I Shutdown, channel 1 & 2: low = amplifier enabled, high = amplifier disabled. See Section 7.3.11 for more information.
SHDN34 7 I Shutdown, channel 3 & 4: low = amplifier enabled, high = amplifier disabled. See Section 7.3.11 for more information.
VCC+ 2 Positive (highest) power supply
VCC– 11 Negative (lowest) power supply