SBOS556D June   2011  – August 2020 OPA171-Q1 , OPA2171-Q1 , OPA4171-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions : OPA171-Q1 and OPA2171-Q1
    2.     Pin Functions : OPA4171-Q1
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information — OPA171-Q1 and OPA2171-Q1
    5. 6.5 Thermal Information — OPA4171-Q1
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
      1. 6.7.1 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operating Characteristics
      2. 7.3.2 Phase-Reversal Protection
      3. 7.3.3 Capacitive Load and Stability
    4. 7.4 Device Functional Modes
      1. 7.4.1 Common-Mode Voltage Range
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Electrical Overstress
    2. 8.2 Typical Application
      1. 8.2.1 Capacitive Load Drive Solution Using an Isolation Resistor
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Functions : OPA171-Q1 and OPA2171-Q1

PIN I/O DESCRIPTION
NAME OPA171-Q1
SOT-23		 OPA2171-Q1
SOIC AND VSSOP
+IN 3 — I Noninverting input
+IN A — 3 I Noninverting input, channel A
+IN B — 5 I Noninverting input, channel B
–IN 4 — I Inverting input
–IN A — 2 I Inverting input, channel A
–IN B — 6 I Inverting input, channel B
OUT 1 — O Output
OUT A — 1 O Output, channel A
OUT B — 7 O Output, channel B
V+ 5 8 — Positive (highest) power supply
V– 2 4 — Negative (lowest) power supply
GUID-1177C77E-708E-4A56-BE62-C975F4A79194-low.gif Figure 5-3 OPA4171-Q1 D and PW Packages
14-Pin SOIC and TSSOP
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