SBOS940B May   2019  – December 2025 OPA818

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics: VS = ±5 V
    7. 6.7 Typical Characteristics: VS = 6 V
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input and ESD Protection
      2. 7.3.2 Feedback Pin
      3. 7.3.3 Decompensated Architecture With Wide Gain-Bandwidth Product
      4. 7.3.4 Low Input Capacitance
    4. 7.4 Device Functional Modes
      1. 7.4.1 Split-Supply Operation (+4/–2 V to ±6.5 V)
      2. 7.4.2 Single-Supply Operation (6 V to 13 V)
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Wideband, Noninverting Operation
      2. 8.1.2 Wideband, Transimpedance Design Using the OPA818
    2. 8.2 Typical Applications
      1. 8.2.1 High-Bandwidth, 100-kΩ Gain Transimpedance Design
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Noninverting Gain of 2 V/V
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Thermal Considerations
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DRG|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.2 Layout Example

OPA818 Layout Recommendation Figure 8-9 Layout Recommendation

When configuring the OPA818 as a transimpedance amplifier take extra care to minimize the inductance between the avalanche photodiode (APD) and the amplifier. Always place the photodiode on the same side of the PCB as the amplifier. Placing the amplifier and the APD on opposite sides of the PCB increases the parasitic effects due to via inductance. APD packaging can be quite large, which often requires the APD to be placed further away from the amplifier than ideal. The added distance between the two device results in increased inductance between the APD and op-amp feedback network (see also Equation 4). The added inductance is detrimental to a decompensated amplifier stability because this amplifier isolates the APD capacitance from the noise gain transfer function. Equation 4 calculates the noise gain. The added PCB trace inductance between the feedback network increases the denominator in Equation 4, thereby reducing the noise gain and the phase margin. In cases where a leaded APD in a TO can is used, further minimize inductance by cutting the leads of the TO can as short as possible. Also, consider edge mounting the photodiode on the PCB versus through the hole, if the application allows.

To improve the layout in Figure 8-10, follow some of the guidelines in Figure 8-11. The two key rules to follow are:

  • Add an isolation resistor RISO as close as possible to the inverting input of the amplifier. Select the value of RISO to be between 10 Ω and 20 Ω. The resistor dampens the potential resonance caused by the trace inductance and the amplifiers internal capacitance.
  • Close the loop between the feedback elements (RF and CF) and RISO as close to the APD pins as possible. This configuration provides a more balanced layout and reduces the inductive isolation between the APD and the feedback network.

Equation 4. N o i s e   G a i n   =   ( 1   +   Z F Z I N )

where,

  • ZF is the total impedance of the feedback network
  • ZIN is the total impedance of the input network

OPA818 Non-Ideal TIA LayoutFigure 8-10 Non-Ideal TIA Layout
OPA818 Improved TIA LayoutFigure 8-11 Improved TIA Layout