SBOS622D July   2018  – May 2025 OPA855

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input and ESD Protection
      2. 8.3.2 Feedback Pin
      3. 8.3.3 Wide Gain-Bandwidth Product
      4. 8.3.4 Slew Rate and Output Stage
    4. 8.4 Device Functional Modes
      1. 8.4.1 Split-Supply and Single-Supply Operation
      2. 8.4.2 Power-Down Mode
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 TIA in an Optical Front-End System
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Optical Sensor Interface
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • Y|0
  • DSG|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.4.2 Layout Example

OPA855 Layout Recommendation Figure 9-12 Layout Recommendation

When configuring the OPA855 as a transimpedance amplifier, take care to minimize the inductance between the avalanche photodiode (APD) and the amplifier. Always place the photodiode on the same side of the PCB as the amplifier. Placing the amplifier and the APD on opposite sides of the PCB increases the parasitic effects due to via inductance. APD packaging can be quite large, which often requires the APD to be placed further away from the amplifier than ideal. Figure 9-13 shows that the added distance between the two device results in increased inductance between the APD and op amp feedback network. The added inductance is detrimental to a decompensated amplifiers stability because this inductance isolates the APD capacitance from the noise-gain transfer function. The noise gain is given by Equation 3. The added PCB trace inductance between the feedback network increases the denominator in Equation 3 thereby reducing the noise gain and the phase margin. In cases where a leaded APD in a TO-can package is used, further minimize inductance by cutting the leads of the TO-can package as short as possible.

Equation 3. N o i s e   G a i n = ( 1 +   Z F Z I N )

where

  • ZF is the total impedance of the feedback network.
  • ZIN is the total impedance of the input network.

The layout shown in Figure 9-13 is improved by following some of the guidelines in Figure 9-14. The two key rules to follow are:

  1. Add an isolation resistor RISO as close as possible to the inverting input of the amplifier. Select the value of RISO to be between 10 Ω and 20 Ω. The resistor dampens the potential resonance caused by the trace inductance and the amplifiers internal capacitance.
  2. Close the loop between the feedback elements (RF and CF) and RISO as close to the APD pins as possible. This closure provides a more balanced layout and reduces the inductive isolation between the APD and the feedback network.

OPA855 Non-Ideal TIA LayoutFigure 9-13 Non-Ideal TIA Layout
OPA855 Improved TIA LayoutFigure 9-14 Improved TIA Layout