SCPS124H September 2006 – March 2021 PCA9534
When an I/O is configured as an input, FETs Q1 and Q2 (in Figure 9-2) are off, creating a high-impedance input. The input voltage may be raised above VCC to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register. In this case, there are low-impedance paths between the I/O pin and either VCC or GND. The external voltage applied to this I/O pin should not exceed the recommended levels for proper operation.