SCPS124H September   2006  – March 2021 PCA9534


  1. Features
  2. Description
  3. Revision History
  4. Description (Continued)
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Resistance Characteristics
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Interface Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Functional Block Diagram
    2. 9.2 Device Functional Modes
      1. 9.2.1 Power-On Reset
      2. 9.2.2 I/O Port
      3. 9.2.3 Interrupt Output ( INT)
        1. Interrupt Errata
          1. Description
          2. System Impact
          3. System Workaround
    3. 9.3 Programming
      1. 9.3.1 I2C Interface
      2. 9.3.2 Register Map
        1. Device Address
        2. Control Register And Command Byte
        3. Register Descriptions
        4. Bus Transactions
          1. Writes
          2. Reads
  10. 10Application Information Disclaimer
    1. 10.1 Application Information
      1. 10.1.1 Typical Application
        1. Design Requirements
          1. Minimizing ICC When The I/O Controls Leds
  11. 11Power Supply Recommendations
    1. 11.1 Power-On Reset Requirements
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Power-On Reset Requirements

In the event of a glitch or data corruption, PCA9534 can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application.

The two types of power-on reset are shown in Figure 11-1 and Figure 11-2.

GUID-9C69E0F5-EA7B-489D-ACEC-BE801281EC5D-low.gifFigure 11-1 VCC Is Lowered Below 0.2 V Or 0 V And Then Ramped Up To VCC
GUID-E7AE7CD3-86D2-4DA9-AF3F-FE27B8571D67-low.gifFigure 11-2 VCC Is Lowered Below The Por Threshold, Then Ramped Back Up To VCC

Table 11-1 specifies the performance of the power-on reset feature for PCA9534 for both types of power-on reset.

Table 11-1 Recommended Supply Sequencing And Ramp Rates(1)
VCC_FTFall rateSee Figure 11-11100ms
VCC_RTRise rateSee Figure 11-10.01100ms
VCC_TRR_GNDTime to re-ramp (when VCC drops to GND)See Figure 11-10.001ms
VCC_TRR_POR50Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV)See Figure 11-20.001ms
VCC_GHLevel that VCCP can glitch down to, but not cause a functional disruption when VCCX_GW = 1 μsSee Figure 11-31.2V
VCC_GWGlitch width that will not cause a functional disruption when VCCX_GH = 0.5 × VCCxSee Figure 11-3μs
VPORFVoltage trip point of POR on falling VCC0.7671.144V
VPORRVoltage trip point of POR on rising VCC1.0331.428V
TA = –40°C to 85°C (unless otherwise noted)

Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and the device impedance are factors that affect power-on reset performance. Figure 11-3 and Table 11-1 provide more information on how to measure these specifications.

GUID-21907428-460E-4DF3-ABFB-4B543E3BE922-low.gifFigure 11-3 Glitch Width And Glitch Height

VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based on the VCC being lowered to or from 0. Figure 11-4 and Table 11-1 provide more details on this specification.

GUID-BB5C9265-29A6-464F-AE12-6466FC1F82EF-low.gifFigure 11-4 VPOR