SCPS131J August   2005  – March 2021 PCA9555

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Device Features
      1. 8.3.1 Power-On Reset (POR)
      2. 8.3.2 I/O Port
    4. 8.4 Device Functional Modes
      1. 8.4.1 Interrupt ( INT) Output
        1. 8.4.1.1 Interrupt Errata
          1. 8.4.1.1.1 INT Description
          2. 8.4.1.1.2 System Impact
          3. 8.4.1.1.3 System Workaround
    5. 8.5 Programming
      1. 8.5.1 I2C Interface
      2. 8.5.2 Register Map
        1. 8.5.2.1 Device Address
        2. 8.5.2.2 Control Register And Command Byte
        3. 8.5.2.3 Register Descriptions
        4. 8.5.2.4 Bus Transactions
          1. 8.5.2.4.1 Writes
          2. 8.5.2.4.2 Reads
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
      1. 9.1.1 Typical Application
        1. 9.1.1.1 Design Requirements
        2. 9.1.1.2 Design Requirements
          1. 9.1.1.2.1 Minimizing ICC When I/O Is Used To Control Led
        3. 9.1.1.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power-On Reset Requirements
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2 Functional Block Diagram

GUID-05AF6613-6EBE-4FFA-8753-38EB7F7B0FFF-low.gif
Pin numbers shown are for DB, DBQ, DGV, DW, and PW packages.
All I/Os are set to inputs at reset.
Figure 8-1 Logic Diagram
GUID-681B6E95-1B64-4900-B069-361109CFBF89-low.gif
At power-on reset, all registers return to default values.
Figure 8-2 Simplified Schematic Of P-Port I/Os