SBASAH0A April   2022  – September 2022 PCM3120-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4.     Thermal Information
    5. 7.4  Electrical Characteristics
    6. 7.5  Timing Requirements: I2C Interface
    7. 7.6  Switching Characteristics: I2C Interface
    8. 7.7  Timing Requirements: TDM, I2S or LJ Interface
    9. 7.8  Switching Characteristics: TDM, I2S or LJ Interface
    10.     Timing Requirements: PDM Digital Microphone Interface
    11. 7.9  Switching Characteristics: PDM Digial Microphone Interface
    12. 7.10 Timing Diagrams
    13. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Serial Interfaces
        1. 8.3.1.1 Control Serial Interfaces
        2. 8.3.1.2 Audio Serial Interfaces
          1. 8.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 8.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 8.3.1.2.3 Left-Justified (LJ) Interface
        3. 8.3.1.3 Using Multiple Devices With Shared Buses
      2. 8.3.2  Phase-Locked Loop (PLL) and Clock Generation
      3. 8.3.3  Input Channel Configurations
      4. 8.3.4  Reference Voltage
      5. 8.3.5  Programmable Microphone Bias
      6. 8.3.6  Signal-Chain Processing
        1. 8.3.6.1 Programmable Channel Gain and Digital Volume Control
        2. 8.3.6.2 Programmable Channel Gain Calibration
        3. 8.3.6.3 Programmable Channel Phase Calibration
        4. 8.3.6.4 Programmable Digital High-Pass Filter
        5. 8.3.6.5 Programmable Digital Biquad Filters
        6. 8.3.6.6 Programmable Channel Summer and Digital Mixer
        7. 8.3.6.7 Configurable Digital Decimation Filters
          1. 8.3.6.7.1 Linear Phase Filters
            1. 8.3.6.7.1.1 Sampling Rate: 7.35 kHz to 8 kHz
            2. 8.3.6.7.1.2 Sampling Rate: 14.7 kHz to 16 kHz
            3. 8.3.6.7.1.3 Sampling Rate: 22.05 kHz to 24 kHz
            4. 8.3.6.7.1.4 Sampling Rate: 29.4 kHz to 32 kHz
            5. 8.3.6.7.1.5 Sampling Rate: 44.1 kHz to 48 kHz
            6. 8.3.6.7.1.6 Sampling Rate: 88.2 kHz to 96 kHz
            7. 8.3.6.7.1.7 Sampling Rate: 176.4 kHz to 192 kHz
            8. 8.3.6.7.1.8 Sampling Rate: 352.8 kHz to 384 kHz
            9. 8.3.6.7.1.9 Sampling Rate: 705.6 kHz to 768 kHz
          2. 8.3.6.7.2 Low-Latency Filters
            1. 8.3.6.7.2.1 Sampling Rate: 14.7 kHz to 16 kHz
            2. 8.3.6.7.2.2 Sampling Rate: 22.05 kHz to 24 kHz
            3. 8.3.6.7.2.3 Sampling Rate: 29.4 kHz to 32 kHz
            4. 8.3.6.7.2.4 Sampling Rate: 44.1 kHz to 48 kHz
            5. 8.3.6.7.2.5 Sampling Rate: 88.2 kHz to 96 kHz
            6. 8.3.6.7.2.6 Sampling Rate: 176.4 kHz to 192 kHz
          3. 8.3.6.7.3 Ultra-Low Latency Filters
            1. 8.3.6.7.3.1 Sampling Rate: 14.7 kHz to 16 kHz
            2. 8.3.6.7.3.2 Sampling Rate: 22.05 kHz to 24 kHz
            3. 8.3.6.7.3.3 Sampling Rate: 29.4 kHz to 32 kHz
            4. 8.3.6.7.3.4 Sampling Rate: 44.1 kHz to 48 kHz
            5. 8.3.6.7.3.5 Sampling Rate: 88.2 kHz to 96 kHz
            6. 8.3.6.7.3.6 Sampling Rate: 176.4 kHz to 192 kHz
            7. 8.3.6.7.3.7 Sampling Rate: 352.8 kHz to 384 kHz
      7. 8.3.7  Automatic Gain Controller (AGC)
      8. 8.3.8  Voice Activity Detection (VAD)
      9. 8.3.9  Digital PDM Microphone Record Channel
      10. 8.3.10 Interrupts, Status, and Digital I/O Pin Multiplexing
    4. 8.4 Device Functional Modes
      1. 8.4.1 Sleep Mode or Software Shutdown
      2. 8.4.2 Active Mode
      3. 8.4.3 Software Reset
    5. 8.5 Programming
      1. 8.5.1 Control Serial Interfaces
        1. 8.5.1.1 I2C Control Interface
          1. 8.5.1.1.1 General I2C Operation
            1. 8.5.1.1.1.1 I2C Single-Byte and Multiple-Byte Transfers
              1. 8.5.1.1.1.1.1 I2C Single-Byte Write
              2. 8.5.1.1.1.1.2 I2C Multiple-Byte Write
              3. 8.5.1.1.1.1.3 I2C Single-Byte Read
              4. 8.5.1.1.1.1.4 I2C Multiple-Byte Read
    6. 8.6 Register Maps
      1. 8.6.1 Device Configuration Registers
        1. 8.6.1.1 PCM3120-Q1 Access Codes
      2. 8.6.2 Page 0 Registers
      3. 8.6.3 Page 1 Registers
      4. 8.6.4 Programmable Coefficient Registers
        1. 8.6.4.1 Programmable Coefficient Registers: Page 2
        2. 8.6.4.2 Programmable Coefficient Registers: Page 3
        3. 8.6.4.3 Programmable Coefficient Registers: Page 4
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Two-Channel Analog Microphone Recording
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Example Device Register Configuration Script for EVM Setup
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Four-Channel Digital PDM Microphone Recording
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Example Device Register Configuration Script for EVM Setup
    3. 9.3 What to Do and What Not to Do
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.11 Typical Characteristics

at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS, TDM slave mode, PLL on, differential input, channel gain = 0 dB, and linear phase decimation filter (unless otherwise noted); all performance measurements are done with a 20-kHz, low-pass filter, and an A-weighted filter

GUID-20201214-CA0I-GS4D-179J-3VQWQ62WL4GZ-low.gif
Differential input
Figure 7-4 THD+N vs Input Amplitude
GUID-20201214-CA0I-6LTR-BH52-J2QDJSSQ7W8F-low.gif
Differential input with AVDD = 1.8 V and VREF = 1.375 V
Figure 7-6 THD+N vs Input Amplitude
GUID-20201214-CA0I-2NP6-2W0F-Q8S6VSKWPDM8-low.gif
 
Figure 7-8 THD+N vs Input Frequency With a –1-dBr Input
GUID-20201214-CA0I-CTP6-F2JF-BFTDDLSLR3JN-low.gif
Single-ended input
Figure 7-10 Input-Referred Noise vs Channel Gain
GUID-20201214-CA0I-X11S-GWL2-C9RZPS0HTP8K-low.gif
Figure 7-12 Power-Supply Rejection Ratio vs Ripple Frequency With 100-mVPP Amplitude
GUID-20201214-CA0I-GJ2D-LR0G-KNBDBD3X1JVR-low.gif
Figure 7-14 Differential FFT With a –60-dBr Input
Figure 7-16 Single Ended FFT With a –60-dBr Input
GUID-20201214-CA0I-JNVK-34BW-VTCDVQFDL15S-low.gif
 
Figure 7-18 PDM Input THD+N vs Input Amplitude
GUID-20201214-CA0I-NMJW-B3JR-DVRCNKFWZXRR-low.gif
 
Figure 7-20 PDM Input FFT With a –60-dBr Input
GUID-20201214-CA0I-LDZW-XLFS-M13WQ8X5RW90-low.gif
Single-ended input
Figure 7-5 THD+N vs Input Amplitude
GUID-20201214-CA0I-DM9P-KWRF-HM2MLTPWZH4N-low.gif
 
Figure 7-7 THD+N vs Input Frequency With a –60-dBr Input
GUID-20201214-CA0I-NJGZ-PQCW-KBWXNBNDTHBH-low.gif
Differential input
Figure 7-9 Input-Referred Noise vs Channel Gain
GUID-20201214-CA0I-CCZN-HR1L-SXPJ0HS2KWXJ-low.gif
 
Figure 7-11 Frequency Response With a –12-dBr Input
GUID-20201214-CA0I-BDVL-KBP5-9LJ7BGK7GDVS-low.gif
Figure 7-13 Differential FFT With Idle Input
Figure 7-15 Single Ended FFT With Idle Input
GUID-20201214-CA0I-ZWQZ-87ZN-H59XG25QVP4S-low.gif
Figure 7-17 Differential FFT With a –1-dBr Input
GUID-20201214-CA0I-CVKN-3GH3-9RJC95MHRJRW-low.gif
 
Figure 7-19 PDM Input THD+N vs Input Frequency With a
–20-dBr Input
GUID-20201214-CA0I-8S0X-3ZBH-JFW8QZMGWCFC-low.gif
 
Figure 7-21 PDM Input Frequency Response With a
–20-dBr Input