SLLSFM0A March 2022 – June 2022 SN6507
The SN6507 has a CLK pin which can be used to synchronize the device with system clock and in turn with other SN6507 devices so that the system can control the exact switching frequency of the device. In SYNC mode, the CLK frequency is divided by two to drive the gates of powerFETs. Figure 9-2 shows the timing diagram for the same.
The device can automatically changes from SYNC mode to the internal or resistor CLK mode, if a valid external clock is not present for a certain period of time (tCLKTIMER). Similarly, when the part transitions from internal or resistor controlled CLK mode to SYNC mode, there will be five CLK cycles delay for external CLK detection.
When the device is in SYNC mode, duty cycle control and SSM are not supported., therefore it's recommended to leave DC pin floating in SYNC mode for reduce the solution size.
Note that it's recommended that VCC pin powers up before CLK pin. Otherwise the initial state of external clock should be high-Z.