SLLS994B February   2010  – July 2015 SN65HVDA1050A-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Power Dissipation Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Operating Modes
        1. 8.3.1.1 Normal Mode
        2. 8.3.1.2 Silent Mode
      2. 8.3.2 Protection Features
        1. 8.3.2.1 TXD Dominant State Timeout
        2. 8.3.2.2 Thermal Shutdown
        3. 8.3.2.3 Undervoltage Lockout and Unpowered Device
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Using the Device With 3.3-V Microcontrollers
      2. 9.1.2 Using SPLIT (VREF) With Split Termination
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Bus Loading, Length, and Number of Nodes
        2. 9.2.1.2 CAN Termination
        3. 9.2.1.3 Loop Propagation Delay
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 ESD Protection
        2. 9.2.2.2 Transient Voltage Suppresser (TVS) Diodes
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 Using the Device With 3.3-V Microcontrollers

The input level threshold for the digital input pins of this device is 3.3-V compatible; however, a few application considerations must be taken when using this device with 3.3-V microcontrollers. The TXD input pin has an internal pullup source to VCC. Some microcontroller vendors recommend using an open-drain configuration on their I/O pins in this case, even though the pullup limits the current. As such, care must be taken at the application level that TXD has sufficient pullup to meet system timing requirements for CAN. The internal pullup on TXD especially may not be sufficient to overcome the parasitic capacitances and allow for adequate CAN timing; thus, an additional external pullup may be required. Care must also be taken with the RXD pin of the microcontroller, as the RXD output of this device drives the full VCC range (5 V). If the microcontroller RXD input pin is not 5-V tolerant, this must be addressed at the application level. Other options include using a CAN transceiver from Texas Instruments with I/O level adapting or a 3.3-V CAN transceiver.

9.1.2 Using SPLIT (VREF) With Split Termination

The SPLIT (VREF) pin voltage output provides 0.5 × VCC in normal mode. This pin is specified for both the SPLIT sink/source current condition and the VREF sink/source current condition. The circuit may be used by the application to stabilize the common-mode voltage of the bus by connecting it to the center tap of split termination for the CAN network (see Figure 15). The SPLIT (VREF) pin provides a stabilizing recessive voltage drive to offset leakage currents of unpowered transceivers or other bias imbalances that might bring the network common-mode voltage away from 0.5 × VCC. Using this feature in a CAN network improves the electromagnetic-emissions behavior of the network by eliminating fluctuations in the bus common-mode voltage levels at the start of message transmissions.

SN65HVDA1050A-Q1 split_pin_stabil_lls994.gifFigure 15. SPLIT Pin Stabilization Circuitry and Application

9.2 Typical Application

SN65HVDA1050A-Q1 New_Typ_App_SLLS994.gifFigure 16. Typical Application Using Split Termination for Stabilization

9.2.1 Design Requirements

9.2.1.1 Bus Loading, Length, and Number of Nodes

The ISO 11898 Standard specifies up to 1-Mbps data rate, a maximum bus length of 40 meters, a maximum drop-line (stub) length of 0.3 meters, and a maximum of 30 nodes. However, with careful network design, the system may have longer cables, longer stub lengths, and many more nodes to a bus. Many CAN organizations and standards have scaled the use of CAN for applications outside the original ISO 11898 standard. They have made system-level trade-offs for data rate, cable length, and parasitic loading of the bus. Examples of some of these specifications are ARINC825, CANopen, CAN Kingdom, DeviceNet, and NMEA200 (see Figure 17).

SN65HVDA1050A-Q1 New_Typ_CAN_Bus_SLLS994.gifFigure 17. Typical CAN Bus

A high number of nodes requires a transceiver with high input impedance and wide common-mode range, such as the SN65HVDA1050A-Q1 CAN transceiver. ISO 11898-2 specifies that the driver differential output with a
60-Ω load (two 120-Ω termination resistors in parallel) and the differential output must be greater than 1.5 V. The SN65HVDA1050A-Q1 device is specified to meet the 1.5-V requirement with a 60-Ω load, and additionally specified with a differential output voltage minimum of 1.2 V across a common-mode range of –2 V to 7 V through a 330-Ω coupling network. This network represents the bus loading of 90 SN65HVDA1050A-Q1 transceivers based on their minimum differential input resistance of 30 kΩ. Therefore, the SN65HVDA1050A-Q1 supports up to 90 transceivers on a single bus segment with margin to the 1.2-V minimum differential input voltage requirement at each node.

For CAN network design, margin must be given for signal loss across the system and cabling, parasitic loadings, network imbalances, ground offsets, and signal integrity; thus the practical maximum number of nodes may be lower. Bus length may also be extended beyond the original ISO 11898 standard of 40 meters by careful system design and data rate tradeoffs. For example, CANopen network design guidelines allow the network to be up to 1-km with changes in the termination resistance, cabling, less than 64 nodes, and a significantly lowered data rate.

This flexibility in CAN network design is one of the key strengths of the various extensions and additional standards that have been built on the original ISO 11898 CAN standard.

9.2.1.2 CAN Termination

The ISO 11898 standard specifies the interconnect to be a twisted-pair cable (shielded or unshielded) with 120-Ω characteristic impedance (ZO). Resistors equal to the characteristic impedance of the line must be used to terminate both ends of the cable to prevent signal reflections. Unterminated drop lines (stubs) connecting nodes to the bus must be kept as short as possible to minimize signal reflections. The termination may be on the cable or in a node, but if nodes may be removed from the bus, the termination must be carefully placed so it is not removed from the bus.

Termination is typically a 120-Ω resistor at each end of the bus. If filtering and stabilization of the common-mode voltage of the bus is desired, then split termination may be used (see Figure 18 and Using SPLIT (VREF) With Split Termination).

Care must be taken when determining the power ratings of the termination resistors. A typical worst case fault condition is when the system power supply and ground are shorted across the termination resistance, which results in much higher current through the termination resistance than the current limit of the CAN transceiver.

SN65HVDA1050A-Q1 New_CAN_Term_SLLS994.gifFigure 18. CAN Termination Scheme

9.2.1.3 Loop Propagation Delay

Transceiver loop delay is a measure of the overall device propagation delay, consisting of the delay from the driver input (the TXD pin) to the differential outputs (the CANH and CANL pins), plus the delay from the receiver inputs (the CANH and CANL) to its output (the RXD pin). A typical loop delay for the SN65HVDA1050A-Q1 transceiver is displayed in Figure 20 and Figure 21.

9.2.2 Detailed Design Procedure

9.2.2.1 ESD Protection

A typical application that employs a CAN-bus network may require some form of ESD, burst, and surge protection to shield the CAN transceiver against unwanted transients, which could cause potential damage to the transceiver. To help shield the SN65HVDA1050A-Q1 transceiver against these high energy transients, transient voltage suppressors can be implemented on the CAN differential bus terminals. These devices help to absorb the impact of an ESD, burst, and/or surge strike.

9.2.2.2 Transient Voltage Suppresser (TVS) Diodes

Transient voltage suppressors are the preferred protection components for a CAN bus due to their low capacitance, which allows for design into every node of a multi-node network without requiring a reduction in data rate (see Figure 19). With response times of a few picoseconds and power ratings of up to several kilowatts, TVS diodes present the most effective protection against ESD, burst, and surge transients.

SN65HVDA1050A-Q1 New_Transient_SLLS994.gifFigure 19. Transcient

9.2.3 Application Curves

SN65HVDA1050A-Q1 Tloop_dom_slls994.pngFigure 20. tLoop Delay Waveform Dominant to Recessive
SN65HVDA1050A-Q1 Tloop_rec_slls994.pngFigure 21. tLoop Delay Waveform Recessive to Dominant