SLLSEX9A December   2016  – February 2020 SN65MLVD206B

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic, SN65MLVD206B
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. Table 1.  Absolute Maximum Ratings
    2. Table 2.  ESD Ratings
    3. Table 3.  Recommended Operating Conditions
    4. Table 4.  Thermal Information
    5. Table 5.  Electrical Characteristics
    6. Table 6.  Electrical Characteristics – Driver
    7. Table 7.  Electrical Characteristics – Receiver
    8. Table 8.  Electrical Characteristics – BUS Input and Output
    9. Table 9.  Switching Characteristics – Driver
    10. Table 10. Switching Characteristics – Receiver
    11. 6.1       Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Power-On-Reset
      2. 8.3.2 ESD Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation with VCC < 1.5 V
      2. 8.4.2 Operations with 1.5 V ≤ VCC < 3 V
      3. 8.4.3 Operation with 3 V ≤ VCC < 3.6 V
      4. 8.4.4 Device Function Tables
      5. 8.4.5 Equivalent Input and Output Schematic Diagrams
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Multipoint Communications
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1  Supply Voltage
        2. 9.2.3.2  Supply Bypass Capacitance
        3. 9.2.3.3  Driver Input Voltage
        4. 9.2.3.4  Driver Output Voltage
        5. 9.2.3.5  Termination Resistors
        6. 9.2.3.6  Receiver Input Signal
        7. 9.2.3.7  Receiver Input Threshold (Failsafe)
        8. 9.2.3.8  Receiver Output Signal
        9. 9.2.3.9  Interconnecting Media
        10. 9.2.3.10 PCB Transmission Lines
      4. 9.2.4 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Microstrip vs. Stripline Topologies
      2. 11.1.2 Dielectric Type and Board Construction
      3. 11.1.3 Recommended Stack Layout
      4. 11.1.4 Separation Between Traces
      5. 11.1.5 Crosstalk and Ground Bounce Minimization
      6. 11.1.6 Decoupling
        1.       (a)
        2.       (b)
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Parameter Measurement Information

SN65MLVD206B pm_drive1_sllsex9.gifFigure 2. Driver Voltage and Current Definitions
SN65MLVD206B pm_diff2_sllsex9.gif
A. All resistors are 1% tolerance.
Figure 3. Differential Output Voltage Test Circuit
SN65MLVD206B pm_test3_sllsex9.gif
A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse frequency = 1 MHz, duty cycle = 50 ± 5%.
B. C1, C2 and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.
C. R1 and R2 are metal film, surface mount, ±1%, and located within 2 cm of the D.U.T.
D. The measurement of VOS(PP) is made on test equipment with a -3 dB bandwidth of at least 1 GHz.
Figure 4. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
SN65MLVD206B pm_drive4_sllsex9.gifFigure 5. Driver Short-Circuit Test Circuit
SN65MLVD206B pm_drive5_sllsex9.gif
A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, frequency = 1 MHz, duty cycle = 50 ± 5%.
B. C1, C2, and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.
C. R1 is a metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.
D. The measurement is made on test equipment with a -3 dB bandwidth of at least 1 GHz.
Figure 6. Driver Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
SN65MLVD206B pm_drive6_sllsex9.gif
A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, frequency = 1 MHz, duty cycle = 50 ± 5%.
B. C1, C2, C3, and C4 includes instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.
C. R1 and R2 are metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.
D. The measurement is made on test equipment with a -3 dB bandwidth of at least 1 GHz.
Figure 7. Driver Enable and Disable Time Circuit and Definitions
SN65MLVD206B pm_max7_sllsex9.gifFigure 8. Maximum Steady State Output Voltage
SN65MLVD206B pm_drive8_sllsex9.gif
A. All input pulses are supplied by an Agilent 81250 Stimulus System.
B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software
C. Period jitter is measured using a 100 MHz 50 ±1% duty cycle clock input.
D. Peak-to-peak jitter is measured using a 200 Mbps 215–1 PRBS input.
Figure 9. Driver Jitter Measurement Waveforms
SN65MLVD206B pm_rec9_sllsex9.gifFigure 10. Receiver Voltage and Current Definitions

Table 11. Type-2 Receiver Input Threshold Test Voltages

APPLIED VOLTAGES RESULTING DIFFERENTIAL
INPUT VOLTAGE		 RESULTING COMMON-
MODE INPUT VOLTAGE		 RECEIVER
OUTPUT(1)
VIA VIB VID VIC
2.400 0.000 2.400 1.200 H
0.000 2.400 –2.400 1.200 L
3.475 3.325 0.150 3.4 H
3.425 3.375 0.050 3.4 L
–0.925 –1.075 0.150 –1 H
–0.975 –1.025 0.050 –1 L
(1) H= high level, L = low level, output state assumes receiver is enabled (RE = L)
SN65MLVD206B pm_rec10_sllsen0.gif
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, frequency = 1 MHz, duty cycle = 50 ± 5%. CL is a combination of a 20%-tolerance, low-loss ceramic, surface-mount capacitor and fixture capacitance within 2 cm of the D.U.T.
B. The measurement is made on test equipment with a –3 dB bandwidth of at least 1 GHz.
Figure 11. Receiver Timing Test Circuit and Waveforms
SN65MLVD206B pm_rec11_sllsen0.gif
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, frequency = 1 MHz, duty cycle = 50 ± 5%.
B. RL is 1% tolerance, metal film, surface mount, and located within 2 cm of the D.U.T.
C. CL is the instrumentation and fixture capacitance within 2 cm of the DUT and ±20%.
Figure 12. Receiver Enable and Disable Time Test Circuit and Waveforms
SN65MLVD206B pm_rec12_sllsex9.gif
A. All input pulses are supplied by an Agilent 8304A Stimulus System.
B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software
C. Period jitter is measured using a 10 MHz 50 ±1% duty cycle clock input.
D. Peak-to-peak jitter is measured using a 200 Mbps 215-1 PRBS input.
Figure 13. Receiver Jitter Measurement Waveforms