SCLS130H December   1982  – February 2025 SN54HC244 , SN74HC244

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Electrical Characteristics – SN54HC244
    7. 5.7  Electrical Characteristics – SN74HC244
    8. 5.8  Switching Characteristics
    9. 5.9  Switching Characteristics – CL = 50 pF
    10. 5.10 Switching Characteristics – CL = 150 pF
    11. 5.11 Typical Characteristic
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Standard CMOS Inputs
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout Guidelines
      1. 8.4.1 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Links
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DB|20
  • NS|20
  • N|20
  • PW|20
  • DW|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The SNx4HC244 octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The SNx4HC244 devices are organized as two 4-bit buffers and drivers with separate output-enable (OE) inputs. When OE is low, the device passes noninverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.

Device Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE(3)
SN54HC244 J (CDIP, 20) 24.38mm × 7.62mm 24.38mm × 6.92mm
W (CFP, 20) 13.72mm × 8.13mm 13.72mm × 6.92mm
FK (LCCC, 20) 8.89mm × 8.89mm 8.89mm × 8.89mm
SN74HC244 DB (SSOP, 20) 7.2mm × 7.8mm 7.2mm × 5.3mm
DW (SOIC, 20) 12.80mm × 10.3mm 12.8mm × 7.5mm
N (PDIP, 20) 24.33mm x 9.4mm 24.33mm × 6.35mm
NS (SOP, 20) 12.6mm × 7.8mm 12.6mm × 5.3mm
PW (TSSOP, 20) 6.5mm × 6.4mm 6.5mm × 4.4mm
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
(3) The body size (length × width) is a nominal value and does not include pins.
SN54HC244 SN74HC244 Logic Diagram (Positive Logic)Logic Diagram (Positive Logic)