SCLS738D September   2013  – October 2023 SN74LV1T04

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Related Products
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Operating Characteristics
    8. 7.8 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Clamp Diode Structure
      2. 9.3.2 Balanced CMOS Push-Pull Outputs
    4. 9.4 LVxT Enhanced Input Voltage
      1. 9.4.1 Down Translation
      2. 9.4.2 Up Translation
    5. 9.5 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Power Supply Recommendations
    2. 10.2 Layout
      1. 10.2.1 Layout Guidelines
  12. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The SN74LV1T04 is a single NOT gate with reduced input thresholds to support voltage translation applications.

Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE(3)
SN74LV1T04 DBV (SOT-23, 5) 2.9 mm × 2.8 mm 2.9 mm x 1.6 mm
DCK (SC70, 5) 2 mm x 2.1 mm 2 mm × 1.25 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
(3) The body size (length x width) is a nominal value and does not include pins.
GUID-88F227B1-5B0E-49FB-A758-A30D8D62C976-low.gif Switching Thresholds for 1.8-V to 3.3-V Translation