SCES406L July   2002  – August 2019 SN74LVC1G18

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
    2. 5.1 Logic Diagram (Positive Logic)
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics, –40 to 85°C
    7. 6.7 Switching Characteristics, –40 to 125°C
    8. 6.8 Operating Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Balanced CMOS 3-State Outputs
      2. 8.3.2 Partial Power Down (Ioff)
      3. 8.3.3 Standard CMOS Inputs
      4. 8.3.4 Over-voltage Tolerant Inputs
      5. 8.3.5 Clamp Diode Structure
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Power Considerations
        2. 9.2.1.2 Input Considerations
        3. 9.2.1.3 Output Considerations
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DBV|6
  • DSF|6
  • YZP|6
  • DCK|6
  • DRY|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

DRY and DSF Package
6-Pin SON
Transparent Top View
SN74LVC1G18 dsf-dry.gif
YZP Package
6-Pin DSBGA
Bottom View
SN74LVC1G18 yzp.gif
DBV and DCK Package
6-Pin SOT-23 and SC70
Top View
SN74LVC1G18 dbv-dck.gif
Not to scale. See the mechanical drawings at the end of the data sheet for package dimensions.

Pin Functions

PIN I/O DESCRIPTION
NAME DBV, DCK, DRY, DSF YZP
S 1 A1 Input Active output selection (LOW = Y0, HIGH = Y1)
GND 2 B1 — Ground
A 3 C1 Input Input A
Y1 4 C2 Output Output Y1
VCC 5 B2 — Positive supply
Y0 6 A2 Output Output Y0

5.1 Logic Diagram (Positive Logic)

SN74LVC1G18 lo_dia_ces406.gif