Product details

Technology family LVC Number of channels 1 Operating temperature range (°C) -40 to 125 Rating Catalog Supply current (max) (µA) 10
Technology family LVC Number of channels 1 Operating temperature range (°C) -40 to 125 Rating Catalog Supply current (max) (µA) 10
DSBGA (YZP) 6 2.1875 mm² 1.75 x 1.25 SOT-23 (DBV) 6 8.12 mm² 2.9 x 2.8 SOT-SC70 (DCK) 6 4.2 mm² 2 x 2.1 USON (DRY) 6 1.45 mm² 1.45 x 1 X2SON (DSF) 6 1 mm² 1 x 1
  • Operating temperature from –40°C to +125°C
  • Supports 5-V VCC operation
  • Inputs accept voltages to 5.5 V
  • Supports down translation to VCC
  • Max tpd of 3.4 ns at 3.3 V
  • Low power consumption, 10-µA max ICC
  • ±24-mA Output drive at 3.3 V
  • Typical VOLP (output ground bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (output VOH undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports live insertion, partial-power-down mode, and back-drive protection
  • Latch-up performance exceeds 100 mA
    Per JESD 78, Class II
  • ESD protection exceeds JESD 22
    • 2000-V Human-body model (A114-A)
    • 200-V machine model (A115-A)
    • 1000-V Charged-device model (C101)
  • Operating temperature from –40°C to +125°C
  • Supports 5-V VCC operation
  • Inputs accept voltages to 5.5 V
  • Supports down translation to VCC
  • Max tpd of 3.4 ns at 3.3 V
  • Low power consumption, 10-µA max ICC
  • ±24-mA Output drive at 3.3 V
  • Typical VOLP (output ground bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (output VOH undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports live insertion, partial-power-down mode, and back-drive protection
  • Latch-up performance exceeds 100 mA
    Per JESD 78, Class II
  • ESD protection exceeds JESD 22
    • 2000-V Human-body model (A114-A)
    • 200-V machine model (A115-A)
    • 1000-V Charged-device model (C101)

This non-inverting demultiplexer is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G18 device is a 1-of-2 non-inverting demultiplexer with a 3-state output. This device buffers the data on input A and passes it to either output Y0 or Y1, depending on whether the state of the select (S) input is low or high, respectively.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This non-inverting demultiplexer is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G18 device is a 1-of-2 non-inverting demultiplexer with a 3-state output. This device buffers the data on input A and passes it to either output Y0 or Y1, depending on whether the state of the select (S) input is low or high, respectively.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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Technical documentation

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Type Title Date
* Data sheet SN74LVC1G18 1-of-2 Noninverting Demultiplexer With 3-State Deselected Output datasheet (Rev. L) PDF | HTML 19 Aug 2019
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Product overview Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 06 Nov 2003
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 18 Dec 2002
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 Jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 May 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 May 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 27 Mar 2002
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dec 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note LVC Characterization Information 01 Dec 1996
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Design guide Low-Voltage Logic (LVC) Designer's Guide 01 Sep 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 May 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

5-8-LOGIC-EVM — Generic logic evaluation module for 5-pin to 8-pin DCK, DCT, DCU, DRL and DBV packages

Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
User guide: PDF
Not available on TI.com
Package Pins Download
DSBGA (YZP) 6 View options
SOT-23 (DBV) 6 View options
SOT-SC70 (DCK) 6 View options
USON (DRY) 6 View options
X2SON (DSF) 6 View options

Ordering & quality

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  • Ongoing reliability monitoring

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