SCES515M December   2003  – November 2022 SN74LVC1T45

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics (VCCA = 1.8 V ± 0.15 V)
    7. 6.7  Switching Characteristics (VCCA = 2.5 V ± 0.2 V)
    8. 6.8  Switching Characteristics (VCCA = 3.3 V ± 0.3 V)
    9. 6.9  Switching Characteristics (VCCA = 5 V ±0.5 V)
    10. 6.10 Operating Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65-V to 5.5-V Power-Supply Range
      2. 8.3.2 Support High Speed Translation
      3. 8.3.3 Ioff Supports Partial Power-Down Mode Operation
      4. 8.3.4 Balanced High-Drive CMOS Push-Pull Outputs
      5. 8.3.5 Vcc Isolation
    4. 8.4 Device Functional Modes
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Unidirectional Logic Level-Shifting Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Bidirectional Logic Level-Shifting Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Enable Times
        3. 9.2.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-E6A7DE58-45FF-4B5F-8F42-AEB61132D0DA-low.gifFigure 5-1 DBV Package,6-Pin SOT-23(Top View)
GUID-C6658232-D102-48F7-A817-2A06FBEF8CA4-low.gifFigure 5-3 DRL Package,6-Pin SOT(Top View)
GUID-DB897361-417B-4410-9445-0605710D6870-low.gifFigure 5-2 DCK Package,6-Pin SC70(Top View)
GUID-FCA4DA31-81F0-4F7C-A304-F66BE414D405-low.gifFigure 5-4 DPK Package,6-Pin USON(Top View)
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME DBV, DCK, DRL, DPK
VCCA 1 P SYSTEM-1 supply voltage (1.65 V to 5.5 V)
GND 2 G Device GND
A 3 I/O Output level depends on VCC1 voltage.
B 4 I/O Input threshold value depends on VCC2 voltage.
DIR 5 I GND (low level) determines B-port to A-port direction.
VCCB 6 P SYSTEM-2 supply voltage (1.65 V to 5.5 V)
(1) P = power, G = ground, I/O = input and output, I = input
Figure 5-5 YZP Package,6-Pin DSBGA(Bottom View)
Legend
Power Input
Input or Output Ground
Table 5-2 Pin Functions
PIN TYPE(1) DESCRIPTION
NO. NAME
A1 VCCA P SYSTEM-1 supply voltage (1.65 V to 5.5 V)
A2 VCCB P SYSTEM-2 supply voltage (1.65 V to 5.5 V)
B1 GND G Device GND
B2 DIR I GND (low level) determines B-port to A-port direction.
C1 A I/O Output level depends on VCC1 voltage.
C2 B I/O Input threshold value depends on VCC2 voltage.
(1) P = power, G = ground, I/O = input and output, I = input