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Product details

Parameters

Technology Family LVC Applications GPIO Bits (#) 1 High input voltage (Min) (Vih) 1.08 High input voltage (Max) (Vih) 5.5 Output voltage (Min) (V) 1.65 Output voltage (Max) (V) 5.5 IOH (Max) (mA) -32 IOL (Max) (mA) 32 Rating Catalog open-in-new Find other Direction-controlled voltage translators

Package | Pins | Size

DSBGA (YZP) 6 2 mm² .928 x 1.428 SOT-23 (DBV) 6 5 mm² 2.9 x 1.6 SOT-5X3 (DRL) 6 2 mm² 1.65 x 1.2 SOT-SC70 (DCK) 6 4 mm² 2 x 2.1 USON (DPK) 6 3 mm² 1.6 x 1.6 open-in-new Find other Direction-controlled voltage translators

Features

  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Available in the Texas Instruments NanoFree™ Package
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65-V to 5.5-V Power-Supply Range
  • VCC Isolation Feature – If Either VCCInput Is at GND, Both Ports Are in the High-Impedance State
  • DIR Input Circuit Referenced to VCCA
  • Low Power Consumption, 4-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Partial-Power-Down Mode Operation
  • Max Data Rates
    • 420 Mbps (3.3-V to 5-V Translation)
    • 210 Mbps (Translate to 3.3 V)
    • 140 Mbps (Translate to 2.5 V)
    • 75 Mbps (Translate to 1.8 V)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
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Description

This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.

The SN74LVC1T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry is always active on both A and B ports and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74LVC1T45 is designed so that the DIR input is powered by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature is designed so that if either VCC input is at GND, then both ports are in the high-impedance state.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 32
Type Title Date
* Datasheet SN74LVC1T45 Single-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation and 3-State Outputs datasheet (Rev. L) Feb. 21, 2017
Selection guides Voltage translation buying guide Jun. 13, 2019
User guides Generic AVC and LVC Direction Controlled Translation EVM (Rev. A) Feb. 18, 2019
Selection guides Little Logic Guide 2018 (Rev. G) Jul. 06, 2018
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
User guides Generic AVC and LVC Direction Controlled Translation EVM May 09, 2017
Application notes How to Select Little Logic (Rev. A) Jul. 26, 2016
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
More literature Design Summary for WCSP Little Logic (Rev. B) Nov. 04, 2004
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application notes Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
User guides Signal Switch Data Book (Rev. A) Nov. 14, 2003
Application notes Use of the CMOS Unbuffered Inverter in Oscillator Circuits Nov. 06, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
User guides LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) Dec. 18, 2002
Application notes Texas Instruments Little Logic Application Report Nov. 01, 2002
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards Jun. 13, 2002
Application notes 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) May 22, 2002
Application notes Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices May 10, 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS Mar. 27, 2002
More literature Military Low Voltage Solutions Apr. 04, 2001
Application notes Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices Dec. 01, 1997
Application notes Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes LVC Characterization Information Dec. 01, 1996
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996
User guides Low-Voltage Logic (LVC) Designer's Guide Sep. 01, 1996
Application notes Understanding Advanced Bus-Interface Products Design Guide May 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
10
Description
Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices
EVALUATION BOARDS Download
document-generic User guide
20
Description

The generic EVM is designed to support one, two, four and eight channel LVC and AVC direction-controlled translation devices. It also supports the bus hold and automotive -Q1 devices in the same number of channels. The AVC are low voltage translation devices with lower drive strength of 12mA. LVC is (...)

Features
  • SMB connector available for high speed operation
  • Ground port available on each header pin to maintain signal integrity
  • DIR and OE have 10K ohm pull up /pull down resistor options
  • Designed to support up to 20 different devices
EVALUATION BOARDS Download
document-generic User guide
199
Description
This EVM provides the user with the ability to evaluate the TL16C750E device and its features. The EVM includes an onboard 3.3-V LDO as well as level translation for processors which operate at a higher voltage rail.
Features
  • Fractional baudrate support
  • 128-byte FIFO depth

Design tools & simulation

SIMULATION MODELS Download
SCEJ231.ZIP (94 KB) - HSpice Model
SIMULATION MODELS Download
SCEM401C.ZIP (99 KB) - IBIS Model
SIMULATION MODELS Download
SCEM545A.TSC (23812 KB) - TINA-TI Reference Design
SIMULATION MODELS Download
SCEM546A.ZIP (7 KB) - TINA-TI Spice Model

Reference designs

REFERENCE DESIGNS Download
Reference design maximizing transimpedance bandwidth for LIDAR and time-of-flight (ToF) applications
TIDA-060025 — This design demonstrates a high-speed optical front-end with a Time of Flight (ToF) distance measurement circuit using a fiber-optic transmission medium, which can be adapted to any type of ToF measurement such as through free space. This design features an industry-leading 2.5-V output linear (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
SimpleLink™ Wi-Fi® CC3200 Module LaunchPad
TIDC-CC3200MODLAUNCHXL The CC3200MODLAUNCHXL is a low-cost evaluation platform which hosts the CC3200MOD. The SimpleLink™ CC3200MOD is a wireless microcontroller (MCU) module that integrates an ARM® Cortex™-M4 based MCU, allowing customers to develop an entire application using a single device. The module (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Monte-Carlo Simulation on AM57x Using OpenCL for DSP Acceleration Reference Design
TIDEP0046 TI’s high performance ARM® Cortex®-A15 based AM57x processors also integrate C66x DSPs. These DSPs were designed to handle high signal and data processing tasks that are often required by industrial, automotive and financial applications. The AM57x OpenCL implementation makes it easy (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Power and Thermal Design Considerations Using TI's AM57x Processor Reference Design
TIDEP0047 This TI Design (TIDEP0047) is a reference platform based on the AM57x processor and companion TPS659037 power management integrated circuit (PMIC).  This TI Design specifically highlights important power and thermal design considerations and techniques for systems designed with AM57x and (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Wide Bandwidth Optical Front-end Reference Design
TIDA-00725 This reference design implements and measures a complete 120MHz wide bandwidth optical front end comprising a high speed transimpedance amplifier, fully differential amplifier, and high speed 14-bit 160MSPS ADC with JESD204B interface.  Hardware and software are provided to evaluate the (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
DSBGA (YZP) 6 View options
SC70 (DCK) 6 View options
SOT-23 (DBV) 6 View options
SOT-5X3 (DRL) 6 View options
USON (DPK) 6 View options

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